[SOLVED] Some MIM capacitor layout problem

[iamgyfan]

Hello everyone,
I want to layout a MIM capacitor with virtuoso and cic018 tech. file.
The LVS rule file says that I have to use ME5 and CTM (capacitor metal, on the top layer) to do that.
But I have some problem with LVS check because I didn't find any appropriate label layer to label a pin on CTM.
Unlike ME1 ME2 ... ME6 have ME_TEXT to label them, there is no label for CTM.

Can someone help me ? Thanks a lot.

 

[DharmaSlice]

The label should still be done in metal pin layer. The CTM is only a CAD layer to tell the manufacturing process that its a capacitor.

 

[iamgyfan]

Thanks for your reply!
But capacitor is a two-port element.
If I draw it with CTM and ME5, there is only ME5 that I can label a pin on it.
(By the LVS rule file, that's the only way that I can layout a MIM capacitor)
That is, where should I label the rest pin, and which layer I could use for it?

Apologize for having so many questions!

 

[adix]

Check where the via connecting CTM with a metal layer is and try to place your label next to it.

 

[iamgyfan]

Finally figure out how to get this.
CTM layer is between ME6 and ME5，I had a wrong thought that CTM is the top layer.
Draw ME5 and ME6 and CTM，and use Via5 to connect ME5 and ME6.
The pin should be labeled on ME5 and ME6.
Though DRC will tell you that these two pins are short, but that's ok.

Thanks for everyone's comment!

 

[erikl]

... use Via5 to connect ME5 and ME6.

Actually, CTM is connected to ME6 by Via5.

Though DRC will tell you that these two pins are short, but that's ok.

... and the DRC rules should be aware of this!

 

[iamgyfan]

Oops. I'll keep that in mind.

Thanks!