Re: Solving setup violations? Why and when we use each techn
Please see my comments in-line.
Hi Eshwar,
Thank you for the reply.
Sizing buffering cloning are the main techniques to resolve setup violations.
Keeping in mind that the delay depends on input slew and output load,
1) We do sizing when there are low drive strength cells in the path and the setup violation is because of bad input slew.
2) We do buffering when the setup violation is because of bad output load.
3) Cloning is done when buffering does not help. I dont know much about it.
[Eshwar]: When a cell of required drive strength is not available in the library, cascoding of cells is done to realize the cell. Pro of this method is Cascoding of cells will have reduced Cin and Cout of the resultant cell. Con of this method is if cell is complex one like AOI, routing congestion will occur at cell level in layout.
This technique is rarely used and generally tool driven...As far as I know magma layout tools does this.
Anyway we need to check the timing histogram ( to see if most of the paths are violating in the same range and the cause is same) and even the placement of the cells in the path. if there is lot of congestion, the tool might have taken detours to violate setup.
[Eshwar]: I agree, netdelay will also impact timing.
I am still not clear about how to resolve setup without impacting hold and viceversa. Please discuss about this too.
[Eshwar]: Setup and Hold are like two pans on a balance. If you do over fixing on one, other one crops up. You need to balance both of them properly through proper analysis of violating paths. There are no direct solutions for this but below fundas will help you to analyze and fix them.
There are three components that you can play with to fix setup/hold violations.
1. Clock Path or Clock Tree.
2. Datapath.
3. Constraints to drive layout tool.
1. Clock Path: If you have a setup violation speedup the launch clock path of flop or delay {Add Buffer} the capture clock path of the flop before this make sure you have sufficient positive setup slack for the next path for which this capture flop acts as a launch flop, Add buffer just before CP pin of capture clock path of the flop not anywhere in the middle of the clock path. If you have a hold violation do vice-versa.
2. Datapath: You can do all above jugglery of upsizing, buffering, cloning, VT swap, re-routing of nets to optimize datapath for setup violation. For hold, just add delay buffer of required value to remove the violation. If paths reporting for setup and hold between two registers are different analyze the paths and add a buffer after the point where both paths diverge.
3. Constraints to drive layout: We can put explicit set_max_delay -max on violating datapaths to direct the tool to concentrate and optimize on highest setup violation seen due to this constraint like below:
set_max_delay -max <some_value_lesser_than_datapath_value> -from <reg1_launch>/CLK -to <reg2_capture>/Q [For setup]
set_min_delay -min <some_value_which_will_not_give_hold_violation> -from <reg1_launch>/CLK -to <reg2_capture>/Q [For hold]
The above procedure is applicable to remap datapath intensive cells like multipliers, adders...etc. This is the way I do to optimize the violating setup paths in DC.
a. Do initial compile with constraints.
b. analyze timing results note down violating setup paths.
b. remove constraints....add set_max_delay constraints.
c. update_timing...DC sees only max_delays to optimize in its timing shell.
d. Iterate or do incremental compile.
e. repeat procedure till DC results are not consistent.
I hope same thing applies for layout also.
Any Queries please let me know...
Thanks,
sowmya.
[Eshwar]:
Regards,
Eshwar.