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Solution to delaying the signal in VHDL code

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koce

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how to delay the signal?

Hi everyone,
I use Altera MAXII CPLD for my project. I program it using Quartus II software and VHDL language. With CPLD I control switches using one global clock signal. For one switch, I want to turn it on not on the rising edge of the global clock but to delay the turning on (10ns for example).
In my VHDL code I use generic type of data.
generic (Tdelay: time:=10ns); I use this constant when I want to delay my signal:
when (clock'event and clock='1')
s1='1' after Tdelay;

VHDL syntax verification is OK but I have a problem when I want to do final compilation.
The error is something like type time does not match string literal
I thing that it is because I use generic type of data.
If someone know the other way of delayin signal using VHDL code please share with me. You will help me a lot!
:D
Thanks
Bojan
 

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how to delay the signal?

Hi,
You must use packages in wich you define the default values.
 

salma ali bakr

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Re: how to delay the signal?

that's very strange
it should work OK
time is already a scalar data type in the VHDL standard
it shouldn't give any troubles if it's used in a generic
try doing a new physical type for time!
watch out also for the spacings in your code, that could be the trouble (but you said syntax was okay)
 

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how to delay the signal?

Hi all,
This happened with me when i simulate with modelsim. This can be resolved by defining all the constants (fonctions....) in a package file that you invoque in the design file using the command use. You must also include this file to the project. When you compile this packages must be compiled first.
 

Iouri

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how to delay the signal?

because this not syntizable code. There is no way software can figure out of to delay the signal, besides 10nS it is a litle bit long, so you should look and adjust your design
 

thuyet

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how to delay the signal?

a small comment, you shouldn't use delay like that because "s1='1' after Tdelay" just used for simulation (modelSim...) . when you write like that , it won't be synthesized in hardware. One way to overcome this : you can pass you signal through some register because each register have a delay, and you can calculate according to you design's specification

Good luck
 

koce

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how to delay the signal?

Thank you very much to all of you for your efforts to help me. You are all so kind!!!
I'll try to delay the signal on hardware way usin the shift registers!
:eek:)
Bojan
 

laststep

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how to delay the signal?

I not sure about this also, but we can delay the signal but adding the #delay right?
just use the command like this
if (clock'evan and clock = 1) then
S1 = #10 '1' ; //assign the data after 10 unit times, depend on ur time scale
#10 S1 = '1'; // get thedata after 10 unit times
 

japoliveira

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Re: how to delay the signal?

Hi! This is my first post in this forum :p

In a CPLD you have at least two ways to delay an input signal, depending on how much time you need for that delay.

The first approach you may consider is using logic cells; for a 10 ns delay 2 or 3 LCELLs are enough (for an Altera EPM7xxx CPLD). Note that this involves direct gate usage with no clock input! Just go to the schematic level and add the LCELLs.

The second approach can be a FIFO. The FIFO length (number of bits) will be dependent on the delay you want and the clock you're using. As an example, if you had a 100MHz clock and wanted a 100ns delay you would need 10 bits. Note here that you may not have enough resources in the CPLD for large delays...

Regards!
 

pankajrangaree1

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Re: how to delay the signal?

in verilog u can assign delays by giving '#' sign and after that u have 2 specify the time unit
 

kvingle

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Re: how to delay the signal?

pardon my verilog ...
But in my knowledge '#' is not meant foe synthesis and koce wants to synthesize the code.better you add the delay of logic cells or shift register.
regards
 

AdvaRes

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Re: how to delay the signal?

koce said:
Thank you very much to all of you for your efforts to help me. You are all so kind!!!
I'll try to delay the signal on hardware way usin the shift registers!
:eek:)
Bojan

You can also use dffs !
 

xtcx

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Re: how to delay the signal?

To my knowledge though,usage of delay say
dout <= '1' AFTER 20ns;
such statements have never been executed. It's purely meant for simulation constructs purpose only it seems. You can feel this in modelsim simulation,but not in real time.....I think
 

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