solution for a memory related issue

[sreevenkjan]

Hi all,

I am looking for a solution.I am currently implementing a image filter.Since the image is a high memory input ,I am currently storing a part of the image in block ram and doing the filtering of the image.I have implemented behav simulation just like the way you have shown in your blog where you access it from block ram.

My question is--is it better if I use nested block RAMs to store the complete image or should I go for ddr.I have never used ddr and have found few tutorials about it.Could you give me some suggestions and ideas and tell me what I should do..

I am using a zynq 7000 soc fpga.my each images are 10KB.

thanks,
Sreeni

 

[syedshan]

hi

I highly recommend go for DDR because it is much faster and, I dont know how much data you have, but you cannot use much resources in FPGA for making memory. It is highly inefficient and impractical way.

Now If you goto DDR and since you are using Xilinx FPGA, then you can use the Xilinx MIG (memory interface generator) for 7-series. It is a little intimidaating at the beginning but you need to start at some point

Any ways join xilinx forum and goto MIG question's community and you will find your answers there as well.

Hope this helps as a beginning step.