soft output viterbi decoder

Similar threads

• X

  VHDL Testbench (Weird output in the simulation)

  • Started by Xenon02
  • Jan 21, 2024
  • Replies: 18

  PLD, SPLD, GAL, CPLD, FPGA Design
• A

  not able get output from OV2640 module

  • Started by aminpix
  • Jun 28, 2023
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design
• J

  ATF1508 - output as open collector with WinCUPL

  • Started by jamesportman
  • Jan 22, 2023
  • Replies: 7

  PLD, SPLD, GAL, CPLD, FPGA Design
• A

  Generating HDMI output with FPGA

  • Started by aminpix
  • Nov 28, 2022
  • Replies: 4

  PLD, SPLD, GAL, CPLD, FPGA Design
• J

  Address decoder - misaligned

  • Started by jamesportman
  • Feb 21, 2022
  • Replies: 4

  PLD, SPLD, GAL, CPLD, FPGA Design