SOC set_clock_latency command problem

[w90043]

I have tried to put set_clock_latency in sdc file but after soc place and route the circuit the clock tree synthesis screw up. My clock pins are not connected directly. In other words, the clock latency is 40% of my clock period. The command I have is as following

set_clock_latency -source 0.0 [all_clocks]

I have multiply create_generated_clock command since its multiply frequency design.

Any help would be appreciated!

Thanks.

 

[f1freak]

Can you elaborate more on how CTS screws up?
The latency value specified is picked by CTS as the skew target.

 

[w90043]

The above waveform shows that there should be same clock signal going to 4 DFF but buffers delayed the clock so my calculation screwed up.