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SOC encounter problem

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siva_7517

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Hi,

I am having problem in encounter when doing timing analysis in the layout. When I choose "Timing -> Timing Analysis" there is a error showing:

Error : Timing graph must be built before running "Report Slacks".

Can anyone help me on this.

Siva
 

aravind

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u must synthesis ur design by timing > synthesis(PKS)
then do timing optimation and the analysis u design
i think this ur problem
have a nice day
 

Kulprashant

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Hi siva,
u first check all the inputs which u import in SoC Encounter and check in the flow where exactly u have to do timing analysis.
In timing analysis for what (is it for setup or hold) and this is all for Encounter tool not for PKS.
u clearly mention where exactly u r doing timing analysis in the flow then i can clarify more.

Prashant
 

aravind

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hi kulprashant,
encounter wont do any synthsis. it have pks , RC for synthesis.
u must work in encounter and then reply.
bye
 

joe2moon

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> I am having problem in encounter when doing timing analysis in the layout. When I choose "Timing -> Timing Analysis" there is a error showing:
> Error : Timing graph must be built before running "Report Slacks".

--> In normal condition, Encounter will "Build timing graph" automatically as needed when select GUI: Timing -> Timing Analysis.

Check the log file to see if there is any other ERROR (or WARN) messages.
Maybe the input database has some problem.
-------------------------------------------------------------------------------------------
[Info Update #1]
-- SOCE has its own physical synthesis engine (called by optDesign) instead of PKS.
PKS is old synthesis engine used inside SOCE.
-------------------------------------------------------------------------------------------
[Info Update #2]
-- Timing anslysis of SOCE can be done in 5 different design stages:
1) Pre-Place
2) Pre-CTS
3) Post-CTS
4) Post-Route
5) Sign-Off
(You can see these options when pull down the Timing-->Timing Analysis menu.)

Pre-Place timing anslysis can be done before the design has been placed.
SOCE can do timing analysis with gate-level netlist before place & optimizaed.
--------------------------------------------------------------------------------------------
 

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