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Synopsys Power Compiler is a simple tool that helps designers achieve a very low power design by replacing multi-bit registers feedback loops with a single clock-gating cell. After a quick review of Power Compiler features and advantages, we will focus on its limitations: a single level of clock gating only, no hierarchical understanding of the design, no ability to use one clock gating cell for several registers with slightly different enabling conditions, etc. Once those limitations and their impact on the quality of result have been well understood with a few design examples, we will determine solutions to get the best results from Power Compiler.