SNR issues in pipeline ADC

[wdd]

hi, all,

I had builded a pipelined ADC, with the first time simulation of
the whole circuit, the SNR is 47.8dB, SFDR=64dB.
which are worse for a 10bit ADC.

The sampling capacitor is 1pf in my circuit, and with the
simulation results of track-and-hold, I think the OTA doesn't
contribute to much noise.
So I don't know what's wrong with the circuit, or what's the
possible defects exist?

Best Regards.
wdd

 

[carlyou]

SNR in pipeline ADC

Have you done the system simulation? You'd better do it to see the max snr you can get.

 

[Shaber_Mezbah]

SNR in pipeline ADC

Pls, let us know about ur amplifire topology.. and some more circuit detail ....

 

[wdd]

Re: SNR in pipeline ADC

Have you done the system simulation? You'd better do it to see the max snr you can get.

i havn't done that. but i think it's unnessary for pipeline ADC

Added after 17 minutes:

Pls, let us know about ur amplifire topology.. and some more circuit detail ....

the amplifier used the telescopic architectrue with gain boost. the whole circuit contains a track-and-hold block(flip-around architecture), every stage outputs 1.5bits.

may i ask a question?
how to choose the values of switch on resistance, like the sampling switch and
the switch used in flip-around branch in the satges? the sampling frequency is 80M.

 

[sunking]

SNR in pipeline ADC

does you set the right option of simulation about the simulator? such as high precision and low step?

 

[wsy979]

SNR in pipeline ADC

1st
1pf sample capacitor for a 10bit ADC is too small. Acording to limit of kt/C noise, the capacitor should be larger than 1.5pf, and this affect SNR a lot.
2nd
I don't know whether you use close-loop OTA or open-loop one, that is important for ENOB of ADCs.