[SOLVED] SMT components on heavy copper PCB

[mtwieg]

Hello, I'm designing a high current DC-DC converter, and will likely need heavy copper traces on the outer layers (like at least 4oz), but I will also need many small low power components. I've seen PCBs with heavy traces, and their surfaces are always "lumpy" due to the thickness/height of the traces. I was wondering if this becomes a problem for assembly of some fine pitched components? I can imagine leaded packages like SOIC could have problems with their leads wanting to be trapped in the valleys between pads instead of sticking on top. Also small passive SMT packages like 0603 might roll off of their pads, or something. And are there significant spacing/width limitations that come with heavy copper that would make fine pitched packages infeasible (like QFN with 0.5mm pitch)?

In general I'm just looking to avoid embarrassing mistakes on a first PCB revision. Thanks in advance.

 

[loosemoose]

one of the biggest problems will be the trace / space that you need to observe. in general it is 0.075mm (3mils) per 1oz of copper. for the 4oz you need 0.3mm (12mils) spacing and tracks. The surface is flat enough for small components, so there should not be any assembly problems. not sure if you use ENIG or HASL for finish.

 

[FvM]

You should request the design rule documents of your PCB manufacturer. 0.5 mm pitch won't work with 4 oz however. It's O.K. for 2 oz, so if you want to combine fine pitch with high current, you have to go for something like all 2 oz multilayer. 2 oz also avoids the problme brought up with thick copper, it has still a plane surface.

There are special techniques combining coppper features of different thichness on outer layers like the "Iceberg" technology. See a brief description together with iceberg and standard thick copper design rules on this manufacturer site.

The previously suggested multilayer sandwich method will most likely achieve good results for standard power PCB designs at lower costs than these exotic methods.

 

[mtwieg]

one of the biggest problems will be the trace / space that you need to observe. in general it is 0.075mm (3mils) per 1oz of copper. for the 4oz you need 0.3mm (12mils) spacing and tracks. The surface is flat enough for small components, so there should not be any assembly problems. not sure if you use ENIG or HASL for finish.

You should request the design rule documents of your PCB manufacturer. 0.5 mm pitch won't work with 4 oz however. It's O.K. for 2 oz, so if you want to combine fine pitch with high current, you have to go for something like all 2 oz multilayer. 2 oz also avoids the problme brought up with thick copper, it has still a plane surface.

There are special techniques combining coppper features of different thichness on outer layers like the "Iceberg" technology. See a brief description together with iceberg and standard thick copper design rules on this manufacturer site.

The previously suggested multilayer sandwich method will most likely achieve good results for standard power PCB designs at lower costs than these exotic methods.

Okay, that's easy enough to follow. It's actually hard to find certain IC functions in packages greater than 0.5mm, which makes things difficult... Using a multilayer 2oz board might get my resistance back down to where I want, but what about the thermal performance of the traces? Some of them will likely need to take 30A DC continuous, and I'm worried that even if I use multiple layers, the inner layers will heat up too much. Also I was hoping to use the copper layers for some amount of heat spreading for power components, will dividing things into multiple layers severely degrade performance, even with lots of thermal vias?

 

[Alan0354]

I am no pcb expert, I would use multi layer of less thickness rather than one thick layer of copper.

Heat generate is proportion to the resistance. The more resistance, you drop more voltage and more power dissipates in the trace and heat up. So the key is to minimize the resistance........wider trace, multiple trace. Don't forget, you need multiple vias if you change layer, that is as if not more important as the width of the trace. You don't want to create local heat spot.

Multi layer is not expensive anymore, use more layer, use plane for the high current, use multiple layer connecting to the output or input pin so you don't create a bottle neck.

Also, layer stack up is important, make sure you have balance layers so the board don't warp.

 

[FvM]

Okay, that's easy enough to follow. It's actually hard to find certain IC functions in packages greater than 0.5mm, which makes things difficult... Using a multilayer 2oz board might get my resistance back down to where I want, but what about the thermal performance of the traces? Some of them will likely need to take 30A DC continuous, and I'm worried that even if I use multiple layers, the inner layers will heat up too much. Also I was hoping to use the copper layers for some amount of heat spreading for power components, will dividing things into multiple layers severely degrade performance, even with lots of thermal vias?

Without knowing your design problem, it's difficult to comment details. 30 A doesn't sound like a particularly high current if you are able to spread it over a respective copper width. FR4 vertical thermal resistance will be still low compared with PCB surface to ambient.

 

[Alan0354]

Lets do a little calculation. conductivity σ of copper is about 6EE7.

R=L/(σA)

so for 6" of 100mil trace of 1oz copper, this means length L=6000mil, width=100mil, thickness is 1.5mil(1oz). R= 6000/(6EE7 X 100X1.5)=6.67EE-7Ω

Passing 30A give 2EE-5V drop. Power dissipated in the 6" trace is W=IV=30X2EE-5=6EE-4W. That's not a whole lot of power.

Please double check my calculation. I just did this really quick. I just make all dimension in same unit.

This is the link I am looking at:

https://en.wikipedia.org/wiki/Electrical_resistivity_and_conductivity

Watch out the vias, use multiple vias, that might be the bottle neck.

 

[FvM]

The calculation isn't correct. 1 oz copper has a sheet resistance of about 0.5 mOhm, so a trace with a length of 60 times the width has 60*0.5 = 30 mOhm. Voltage drop at 30A is 0.9V, power dissipation 27 W.

 

[keith1200rs]

I think the error is that resistivity should be on the top of the right hand equation, not the bottom. Higher resistivity should mean higher resistance not lower.

Keith

 

[Alan0354]

I think the error is that resistivity should be on the top of the right hand equation, not the bottom. Higher resistivity should mean higher resistance not lower.

Keith

That is conductivity σ, which is 1/ρ where ρ is resistivity. But I think I found my problem, the number given in the link is in meter, I have to translate to mils.

With the new calculation, it's 26.5mΩ, close to what you have.

 

[FvM]

The unit of conductivity is S/m not S/mil. Please apologize that I'm not used to calculate material parameters in imperial units and thus don't want to dive deeper into it.

 

[Alan0354]

The unit of conductivity is S/m not S/mil. Please apologize that I'm not used to calculate material parameters in imperial units and thus don't want to dive deeper into it.

Yes, you are right, I just re post it.

 

[Bryan-PCB]

3 mil space/width and 2 OZ can not be build with a lot of PCB manufacturer.

 

[Alan0354]

Use multiple 1oz planes. Use like 3 to 4 planes for each high current signal.

 

[FvM]

Use multiple 1oz planes. Use like 3 to 4 planes for each high current signal.

Not to repeat previous detail considerations. Typically the trade-off ends up with 2 oz layers.

 

[mtwieg]

Multiple 2oz layers sounds like the way to go then. If anything that's nice because having the extra layers will make routing everything else a lot easier.

Thanks all.