SMPS unstable output

[StevenHart]

Hi,

I have an unstable 50V output from my SMPS and I am finding it hard to explain why.
I am quite new to SMPS design and have inherited this design but I believe there is a flaw in the design.

I am using two LTC3862-2 in a master-slave configuration to generate a 50V, 52.5V,85V output.

The output voltage is stable at 85V but at 52.5V and 50V the output of the SMPS becomes unstable.
The output voltage is perfectly stable at 50V when there is NO load, but applying a load then causes the output to become unstable.

Here is the schematic for my SMPS. There are a few enable pins going to a microcontroller to alter the potential divider feedback.

According to the datasheet, for a multiple device topology, the following application should be used...

The main difference I can see is my 'ITH' pins are connected separately. I am also not using 100k resistors between feedback pins, as this is quite a sensitive line, could this be having an affect?

Despite the differences, I do not believe this is the root cause though. I measured the output voltage of the 'ITH' pin, and the voltage was just as unstable as the output, varying between Current limit and overload conditions. Also probing the 24V supply to the device and the inductors, an approx 1V drop could be observed. The volt drop can be seen at the PSU which points at the load. Both of these instabilities were in line with the output voltage instabilities. This lead me to the gate drive behavior...

Blue - Load demand (used as trigger point)
Red - Output Voltage (AC coupled)
Green - Gate 1, of master device
Gold - Gate 1, of slave device

It can be seen from the gate behaviour that something is telling the gate to drive a bit harder/longer (green arrow), thus increasing the output voltage (red arrow). This is then compensated with no gate driving condition on the next load demand (blue arrow).

What could be causing this decision?

The same trace for the 85V shows a very consistent output (red), with consistent gate drive behaviour...

Does anybody have any ideas what is causing this?
Any help would be appreciated. I don't what else to check or where else to go from here

Thanks,

 

[KlausST]

Hi,

please show your PCB layout.

Klaus

 

[dick_freebird]

From the narrow duty cycles shown I wonder if this is a min on time / max on time problem that is "breaking the loop" (or just "winding it up").

The character of instability holds clues. A small signal instability ought to look like a sine wave oscillation, while "limit cycle" issues will look bistable or relaxation-oscillator (sawtooth) and likely roll on abruptly with external conditions.

 

[Easy peasy]

RFI getting into the power source .... look at the Vin at the same time ....


also, you have lots of caps on the o/p, but none by the input inductors ?

 

[StevenHart]

Thanks for all of the replies.

The PCB is a 4 layer stackup with 2oz copper on each layer.

This is the PSU PCB of a modular design so the input caps cannot be seen in the layout or on the schematic.
Although modular, the input caps are as close as possible to the board to board connectors. Total length is < 15mm from input caps to smps.
The input caps are shared with another Modular PSU...

Hope this helps,

 

[StevenHart]

RFI getting into the power source .... look at the Vin at the same time ....


also, you have lots of caps on the o/p, but none by the input inductors ?

This is a great shout. As mention I have measured the 24V supply, Vin, and can see a voltage drop. The voltage drop also seems inconsistent and aligned to the load demand to the PSU. This lead me on to the check the gate behaviour, but maybe you have a different though process?

--- Updated Jun 18, 2021 ---

From the narrow duty cycles shown I wonder if this is a min on time / max on time problem that is "breaking the loop" (or just "winding it up").

The character of instability holds clues. A small signal instability ought to look like a sine wave oscillation, while "limit cycle" issues will look bistable or relaxation-oscillator (sawtooth) and likely roll on abruptly with external conditions.

I believe you are right. I have found this almost confirming your theory...

If the controller enters DCM, this explains the skipped pulses and also confirms the inductor current has been reduced lower than the minimum on time (290ns).
This suggests that my inductor is too larger?
Due to the large range of this PSU (50V - 85V), the inductor was selected to suit. As mentioned, the output is stable at 85V but maybe the inductor value is just not appropriate at 50V!?

If indeed the minimum on time has been met, could you suggest how I go about solving that?
Does that suggest the SMPS controller does not like the pulsed nature of the load?

 

[KlausST]

HI,

the input caps cannot be seen in the layout or on the schematic.

You can not run an SMPS without local bulk and fast capacitors.

Although modular, the input caps are as close as possible to the board to board connectors. Total length is < 15mm from input caps to smps.

This won´t work. You need at least fast capacitors and medium sized bulk capacitors on the SMPS PCB.

Klaus

 

[mtwieg]

The main difference I can see is my 'ITH' pins are connected separately. I am also not using 100k resistors between feedback pins, as this is quite a sensitive line, could this be having an affect?

You should really connect the Ith pins together per the datasheet recommendations. The datasheet suggests 100 ohms between each FB/Ith pin, not 100k.

What's the time scale in your plots? Milliseconds?

From personal experience with LT controllers, operating at very light load and then applying a pulsed load can give odd-looking transient behavior. Their controllers often enter pulse-skipping mode or burst mode in order to improve light load efficiency. The transitions between these different modes can look a bit weird sometimes. But that behavior isn't a form of instability.

If you have multiple paralleled controllers, and they are not always operating in the same mode, then the behavior may be even stranger. Joining their Ith pins should mitigate that a lot.

 

[StevenHart]

HI,

You can not run an SMPS without local bulk and fast capacitors.
This won´t work. You need at least fast capacitors and medium sized bulk capacitors on the SMPS PCB.

Klaus

Thanks for you're reply Klaus. I would agree that having little/no input capacitors would cause the SMPS not to work. However, as mentioned this SMPS works with an 85V output.

The modular design with the input/bulk capacitance off board, placed as close to the board to board connectors works. I have 2 other PSU SMPS boards producing out put voltages ranging between 10V-24V and 185V. These work and produce a stable and reliable output.

I do not believe having the bulk capacitance off board to be the problem

 

[StevenHart]

What's the time scale in your plots? Milliseconds?

Yes. The timescales are in milliseconds.

You should really connect the Ith pins together per the datasheet recommendations. The datasheet suggests 100 ohms between each FB/Ith pin, not 100k.

What's the time scale in your plots? Milliseconds?

From personal experience with LT controllers, operating at very light load and then applying a pulsed load can give odd-looking transient behavior. Their controllers often enter pulse-skipping mode or burst mode in order to improve light load efficiency. The transitions between these different modes can look a bit weird sometimes. But that behavior isn't a form of instability.

If you have multiple paralleled controllers, and they are not always operating in the same mode, then the behavior may be even stranger. Joining their Ith pins should mitigate that a lot.

I have made the modifications to my SMPS to comply with the datasheet. Sorry, I'm not sure why I said100K instead of 100R.

The mods have made a huge difference. The output voltage is now gives a 'stable' and consistent output of 50V at the lighter loads...
Un-Modified

Modified,

The gates of both master and slave devices now behave the same however, at the heavier/larger load demands the output voltage seems to just as 'unstable'...

I am not sure how the modifications I have made can improve things so much at the lighter loads and have made such a dramatic affect on the heavier loads.
Does anyone else have any theories on what I have done wrong or what I am missing?

From your past experience @mtweig, sounds like you have run into similar problems. How did you get around the LT device entering pulse-skipping mode?

 

[KlausST]

Hi,

I have made the modifications to my SMPS to comply with the datasheet

I am not sure how the modifications I have made can improve things so much at the lighter loads and have made such a dramatic affect on the heavier loads.
Does anyone else have any theories on what I have done wrong or what I am missing?

If you tell us what modfications exactly you made....we can discuss about it.

Klaus

 

[StevenHart]

The modifications I made were to connect the ITH pins of both devices via a 100R resistor as per the datasheet.

 

[mtwieg]

I am not sure how the modifications I have made can improve things so much at the lighter loads and have made such a dramatic affect on the heavier loads.
Does anyone else have any theories on what I have done wrong or what I am missing?

An exact analytical explanation is probably not worth the time to investigate. But with the Ith pins disconnected from each other, you basically have two separate controllers with their own internal states. In general, that's just messier and can lead to unstable behavior (especially if the controllers are nonlinear).

The Ith voltage usually determines the operating mode of the controller. Can you redo those measurements, but with one of the gate traces replaced with the Ith voltage (of the "master," if there is one)? And maybe zoom in to 5ms/div so we can see the behavior during the pulses more clearly.

From your past experience @mtweig, sounds like you have run into similar problems. How did you get around the LT device entering pulse-skipping mode?

If you post the waveforms with the Ith voltage, I think it will be much easier to explain.

 

[StevenHart]

Thanks for your reply @mtwieg.

But with the Ith pins disconnected from each other, you basically have two separate controllers with their own internal states. In general, that's just messier and can lead to unstable behavior (especially if the controllers are nonlinear).

I gathered this was the case after seeing the difference in behaviour. That was a really useful tip.

I repeated the test as requested, and swapped out gate 1 of the slave device for the ITH pin on the master device. The traces are as follows;
Blue - Load demand (used as trigger point)
Red - Output Voltage (AC coupled)
Green - ITH Voltage, of master device
Gold - Gate 1, of master device

Trace taken with 100us/div. The ITH pin fluctuates between all three conditions, according to the datasheet;
0.4V - 0peak,
1.2V - Current limit,
2.6V - Overload Condition

These 2 waveforms, taken with 2ms/div, show an overload condition but have very different profiles. What do you expect this means?

A current limit condition with again a very different wave profile.

Could the profile of the ITH be indicating something?

I would love to hear you thoughts and gain some of your knowledge around this issue

Hope the scope traces help and let me know if there is anything else you may need.

Thanks,

 

[mtwieg]

One thing that frequently irks me is that the error amplifier output (Ith in this case) is often allowed to swing beyond far outside the range where it's actually regulating the output. The datasheet mentions this:

A buffered version of the output of the error amplifier determines the threshold at the input of the current comparator. The ITH voltage that represents zero peak current is 0.4V and the voltage that represents current limit is 1.2V (at low duty cycle). During an overload condition, the output of the error amplifier is clamped to 2.6V at low duty cycle, in order to reduce the latency when the overload condition terminates [why we allow it to swing that high is for us to know, and you to regret].

Consider a scenario:
1. Load current increases to be slightly above the max Iout the controller can provide
2. Vout drops below regulation point.
3. Ith rises until the max output current is reached
4. Vout continues to drop slowly (depends on how much the load exceeds the max Iout)
5. Ith continues to rise. This doesn't actually result in any more output current though. It will eventually clamp to some voltage.
6. Load drops suddenly.
7. Vout rises rapidly to its setpoint.
8. Ith starts falling, but because it rose far above the max current point, it will take a while for it to actually fall enough to start reducing the output current.
9. Vout continues to rise.
Depending on various factors, a couple different things can happen next:
10a. Vout overshoots to the OVP limit of the controller before Ith can assert proper control. Controller immediately stops switching and enters a soft start. If any more load pulses occur before ss rises, you the Vout regulation during that pulse will be even worse (though it may not overshoot either).
10b. Ith falls and lowers Iout before the OVP occurs.

Looks like 10a is definitely happening in scope capture #3, while 10b happens in #2 and #4. Probing the ss pin can confirm this. It's possible that sometimes only one controller trips its ss at a time (though if their Ith pins are connected it shouldn't matter much...). This behavior arises when things are "just right." If you were to decrease or increase the load much, you should not see the OVP occur at all.

The Vout overshoot can, in theory, be as high as:
Vos = Iout(max) * Trecover / Cout
So there's a few obvious workarounds:
1. Decrease the max Iout of the converter. This will decrease the Vos, but Vout will drop more during load pulses.
2. Increase Cout. No real downside, except the extra bulk.
3. Decrease Trecover:
3a. Increase the impedance of the compensation network. Might not be possible without other stability issues arising.
3b. Implement your own clamp on Ith. Tricky to know what the right voltage is though, since the relationship between Ith and output is never described in detail.

Alternatively:
4. Increase the max Iout of the converter so that it doesn't never goes into overload at all (at least during nominal load transients). I prefer this approach, but it's not always practical.

 

[StevenHart]

Thank you so much for the replies.
This is exactly the help I was looking for from people more experienced than me using SMPS .

@mtwieg, you've made so many amazing suggestions that all sound like they will help.
I'll go away, work through them and keep you updated on my progress.

Thanks for the help

 

[mtwieg]

You're welcome. I'm guessing you found that the soft start was occurring after some of the pulses? Let me know if you're able to get any solutions working.

Linear Tech/Analog make great stuff, but they optimized for more mundane use cases. Pulsed applications like this are a blind spot for them. Usually it is possibly to get them to work how I want, but finding the solution is sometimes very difficult because their datasheets don't really describe their internal operation in detail. In some cases I'll go for a TI/National Semi controller simply because their datasheets give that extra detail, even if it lacks some cool features that the LT part has.