Not so much a thing for digital, but a big deal for analog.
Consider a case where (say) you have an "edgy" process
flirting with impact ionization at shorter L. Your modeling
folks might manage to express this "distribution" properly.
Or not.
In the better case, that they do, you might see the "drain
curl" affect your op amp gain stage. As Av=gm*Ro, this will
be a factor of 3-10 (10-20dB) degradation to your stage
gain at higher drain voltage.
If you are tasked to make a 70dB AVOL op amp and this
gives you 50dB, even cascoded, your only next choice is
to move to a multiple-gain-stage topology. This is not only
larger by transistor count, it's also likely much more difficult
(and needful of much greated compensation-capacitor area)
to stabilize.
Now the question is not only SPICE corners - here you
only ask for realism / "fair warning". The real question as
OP asked, is about process control of device attributes.
For an analog application designers would really like drain
linearity - not really a top-line process control param,
more like something you'd get at by meta-analysis (like
a pair of ID-VD curves in subthreshold where you live,
looking at whether ID is constant slope or curved / kinked).
I haven't seen this depth in WAT data / programs myself.
But I have been surprised on occasion by the effects
that go unmodeled, ruining performance relative to
simulated.
If your process control had a better grip on Leff, on
spacer / LDD / halo strength at suppressing II, the
"drain curl" might be suppressed and enable much better
/ smaller analog block design (or at least push out the
"pain threshold"). Maybe your analog blocks can make
75dB (WC) rather than 40dB and now applications up
to 70dB (say, for gain error in A=100 CL) are able to
use the simplest, smallest op amp design instead of a
2V transistor count, 4X area two-gain-stage design.
In cases where this dominates (like say a ROIC with
a million pixels each with its own TIA, and a demand
for high photon-to-bits linearity across a 12-bit range)
the effect could be not just die size, but success or
failure - die size being "pinned" by the detector-plane
design, that you're told to accept. Can you fit 20
transistors and 5pF of MOS cap in the pixel extents?
While getting TIA gain consistent with a sub-LSB
(12 bit) gain error?