Small doubt

Hello all,

I am a beginner in VHDL. I have just started getting myself acquanited with the tool.

What is the difference between VHDL code and bit file?

I know this is a very basic question, but still I am unaware of this ! Hope I get this answered.

Thank you.

VHDL (or verilog) files are the sources of your project, together with the constraints files. If you compile (synthesize) these files to a certain architecture (FPGA) you will get a bitfile for the targetted FPGA.

Thank you ! I understood the difference .