[SOLVED] SLV into System Generator Block

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ravics

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How can I input std_logic_vector into system generator blocks? Constant block supports fixed, boolean & dsp instructions. Is there any way to force slv as input to another sysgen blk?
 

I'm not sure I understand your question... any time you us a multi-bit bus in SysGen, it will be std_logic_vector. Otherwise, you can likely meet your needs using a black box.
 
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    ravics

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