Slight delay for switching on upper fet of two transistor forward converter?

[treez]

I am designing a two transistor forward converter where the upper fet is driven by a pulse transformer, (fron the controller's gate drive output) but the lower fet is driven on straight from the controller's gate drive output , with no pulse transformer.

........because of leakage in the pulse transformer (its too expensive too wind for the super low leakage required in the pulse transformer)......i intend to put a 1us delay in the track to the lower fet's gate.......in this way, the top fet will come on first....but will suffer no turn-on switching loss as the bottom fet will not yet be on.....the lower fet comes on 1us later, and takes all the switch-on switching loss, but it doesnt matter because the lower fet doesnt have pulse transformer drive and so is fast switched.

The delay will mean the upper fet is also first to turn-off, meaning it will unfortunatley take all the switch-off switching loss, but this is not so bad, because there will be a PNP turn off transistor at the gate of the upper fet....so its switch-off will not be delayed by the pulse transformer's leakage.

Do you think this is a good method?....the 1us delay for the lower fet drive will come via an RC followed by a gate driver chip...the RC being set for the 1us delay.

The converters switching frequency is 85KHz.....do you think this 1us delay will adversely effect the feedback loop?

 

[BradtheRad]

When current builds through a coil, and then the coil is disconnected, it wants to generate high voltage in order to keep current flowing. There is risk of harm to components.

On the other hand if your 1 uS dead time is soft enough, then the coil might not send out such a high voltage spike.

Or else you might consider installing an RC snubber across the coil? Because a diode cannot be used in this situation.

I could be wrong.

 

[treez]

When the upper fet is turned on, the lower fet will initially be off, so no current will flow in the primary, so there should be no spike voltage......i am not sure if this is to what you have made reference, my apologies if it wasnt

 

[BradtheRad]

If the coil is not conducting when you break the loop, then no problem.

If the coil has current going through it, then it might generate a spark (or at least high voltage) when the loop is broken.

I don't know if it will do this in your layout before 1 uS goes by. (I guess I'm not even sure if a diode takes up 1uS to turn on in a similar situation.)

A high-voltage spike is a possibility that always needs to be considered when switching current through a coil.

 

[mtwieg]

If the coil is not conducting when you break the loop, then no problem.

If the coil has current going through it, then it might generate a spark (or at least high voltage) when the loop is broken.

I don't know if it will do this in your layout before 1 uS goes by. (I guess I'm not even sure if a diode takes up 1uS to turn on in a similar situation.)

A high-voltage spike is a possibility that always needs to be considered when switching current through a coil.

What you're describing shouldn't be a problem for a two switch forward converter, regardless of switch delays, due to the external clamping diodes. The primary is inherently clamped to the DC input voltage regardless of the FET operation.

treez, I can see some good reasoning behind delaying the lower gate. If you know that one FET is going to have slower switching speed, then it makes sense to offset the switching losses to the other FET, thereby lowering overall losses. But I think leakage and magnetizing inductance will reduce the effectiveness of this approach. For example, after the ON period (both FETs on), if the upper FET turns off first, then the primary voltage will be clamped to approximately zero (one diode drop). This means that the magnetizing/leakage current will freewheel and not decrease, due to the low clamping voltage. By the time the lower FET turns off after 1us, all that current will still be there, and that lower FET will have to commutate that current, and it will see switching loss because of that. Of course, this is just magnetizing current, which should be much lower than the peak primary current, so this energy loss should be substantially less than the upper FET's turn off loss.

In the end I think you will see some benefit in terms of overall efficiency, though it might be small. Running the numbers in a spreadsheet would probably be a good idea. Also, 1us sounds like a very long delay. Even a cheap GDT should be able to switch a midsized FET in a couple hundred ns. In practice you should try to minimize the delay in order to relieve stress on the diagonal clamping diodes (the longer the delay, the longer they will have to freewheel the magnetizing current).

As for loop response, yes delay matters. Just calculate what the equivalent phase shift at your intended crossover frequency is. If your crossover frequency is low, then it should be negligible (like a few degrees).

 

[BradtheRad]

What you're describing shouldn't be a problem for a two switch forward converter, regardless of switch delays, due to the external clamping diodes. The primary is inherently clamped to the DC input voltage regardless of the FET operation.

I defer to mtwieg's statement. I was not sure about the current paths available.

The pulse transformer idea is worth a try. I see a thread here about the problem of getting the upper mosfet to turn on and off properly. The poster says he destroyed devices while trying.

https://www.edaboard.com/threads/90160/