Slicing DSP block in Zynq FPGA. Is it possible

[Zerox100]

Dear my friend,

Today I bring up with new question.

Is it possible to Slice DSP block in Zynq FPGA?

Could anybody answer please

Thx

 

[dpaul]

Is it possible to Slice DSP block in Zynq FPGA?
Your question is not clear to me.
For e.g. in a Zynq based 7 series Xilinx FPGA, the DSP48E1 Slice (containing many basic elements such as adder, mult, etc.) is one basic DSP unit. In you design you can instantiate the DSP48E1 Slice.

https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf

 

[Zerox100]

I want to use a 18x25 mutiplier as two 8x8 mutiplier;; if it is possible????

 

[dpaul]

I don't think it is possible because the operand width is 25x18 in the DSP48E1.

 

[TrickyDicky]

The Accumulators in the DSP slice can be run in SIMD (single instruction, multiple data) mode, but this prevents the use of the multiplier.