Slew Rate simulation Dc offset

[mirror_pole]

Hey guys,

Im designing a full differential op amp in cadence and want to test the slew rate. Therefore i configured it as a unity gain buffer using feedback resistors. After applying a large signal input step i notice that there is a Dc offset. If i apply a positive input step it doesnt start at 0 Volts where it should be. Same goes if i apply a negative step. Im pretty unexperienced and would like to know the reason

 

[deep_sea]

Usually differential circuits work with CMFB. In simulation, you can use a switch with DC "1" and AC "0" so that your input and output have the same DC level.
take care that if your opamp is high impedance output unless you have a buffer output. Ensure that feedback resistors are large enough to avoid loading effect. One way also to use resistors with large "AC" value and small "DC value" to have the same DC level.

 

[frankrose]

Sorry, but the input large step is differential or common mode step? Not obvious for me.

 

[mirror_pole]

Hey, i apply a voltage step at the non inverting input, the other input has just Vcm.

 

[dick_freebird]

Many simple op amps have a very limited input
common mode range, be sure that you are
seeing loop-closure at both ends of the common
mode (VICM) and differential signal ranges.

 

[frankrose]

Then that is your issue. By this way you changed the differential and common mode input component at the same time. Test with constant common mode input voltage and change both inputs at the same time in different direction with same amplitude.

 

[mirror_pole]

no wait sry i lied..ive used an ideal ballun so a applyed the voltage step as a differential signal

 

[frankrose]

Don't lie, that is simply bad. Have you checked that any half circuit of the opamp doesn't leave normal active region? Headroom of input/output is bigger than the voltage level you apply?

 

[FvM]

Your initial post sounds just confused. Offset is a DC quantity, not measured in transient simulation. Please give a clear description of your test setup and what you are exactly seeing.

 

[mirror_pole]

Thanks for the replies guys and im sorry for not being clear. To be honest im confused myself but ill try to explain it more clearly. I apply a voltage step of +0,6 Volts and -0.6 Volts to measure the positive and negative slew rate. As already said im using a fully differential OTA in voltage follower configuration. For example When i apply the transient step i expect the voltage to rise starting at 0 Volts, but it starts at a few mV. I attach the SImulation result.
Also what could be the reason for this little overshoot?

 

[FvM]

Looks normal. We see clipped output, not offset.

What makes you think the amplifier can process zero input voltage? Why not negative input? We need to see a schematic to understand.

 

[mirror_pole]

Hey FvM im not sure actually. I saw other simulation results in some books so i thought that it has to look that way all the time. I also attach the result with negative step. Looks pretty much symmetrical i would say. The output stage of the diff amp is in push pull configuration using additional cascode transistors.
Here the schematic https://www.semanticscholar.org/pap...dc5e9204b0b80f8d1d6349db65b44964a868/figure/1

Its the topology in figure 2

 

[FvM]

We also need the test setup to understand how clipping occurs.

 

[frankrose]

If you can annotate the transient or DC node voltages to your schematic when t=0 or Vin.d=0V it will help a lot. I think offset can be measured in transient analysis too, but it can easily happen that this offset actually is coming from a gain error and connected to one of your feedback system, I mean maybe your common or differential mode gain is very low somehow when Vin.d=0V. I guess you haven't run mismatch, monte carlo analysis which is normally used to find offset. Share more info, please.