[SOLVED] Sizes of PMOS and NMOS

[ishould]

I'm not sure if this is where I'm supposed to post this, but here it is anyway. This'll probably be really easy

"Consider a NAND gate with NMOS and PMOS sizes of .5um/.25um and .75um/.25um respectively" They go on to say that they're sized this way to make the resistances equal, and the rise and fall times are approximately equal in a worst-case scenario. When I calculate the effective resistances however, they aren't nearly the same, so I'm obviously doing it wrong. I thought PMOS has to have ~3x the width of the NMOS, and in this case it's only 1.5x.
Can someone explain it to me?

-ishould

 

[leo_o2]

In case of "NAND", two NMOSs are series connected and two PMOSs are paralleled. So it is different from simply interver (PMOS has 3x w/l of NMOS's w/l)

 

[ishould]

I know that much, I just don't understand the way they sized their's

 

[ducvilla]

Someone in the forum said that:" The die size and power consumption must be optimized, it had better that let the rise time is equal to the fall time, also trying to balance the logic gates to ensure fast rise and fall times in various logic conditions so as to elilminate race conditions and static hazards."
Base on the size of Pmos and Nmos, the rise time/fall time is different. PMOS should be 2.5 or 3 times larger than NMOS because electron mobility is 2.7 faster than hole mobility.
Regard.

 

[babaduredi]

Hi ishould,
The sizing is correct. Consider this : In NAND gate, when output is zero, both NMOS must be on as they are in series. Hence if we assume path resistance to be R, each NMOS should have resistance R/2. Similarly for PMOS, when output is one, any one PMOS must be on in worst case(both also can be ON). Hence for same path resistance R, each PMOS is designed to have resistance of R(considering worst case scenario). Now we know that (Wp/Wn) \[\approx\] 3 (Rn/Rp), hence Wp\[\approx\]1.5 Wn.

Hope this clears your doubt

 

[ishould]

Ooh, I think I understand now. Thanks babaduredi

 

[muffassir]

hi Ishould,

To have a detailed approach as given by Babaduredi,,of as to why the sizes are like that, and u can also see to work them even at very low voltages STRANGE!!,,,,these all are beautifully explained in the book 'DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE ' 2ND E D I T I O N by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje. L

I recommend this book to read in depth to understand the beauty of digital design....

 

[ishould]

I have the fourth edition of that book