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# Size consideration in designing current mirror

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#### Julian18

##### Full Member level 3
Hi, there,
What is the size consideration(MOSFET) in designing the garden-variety current mirror? I remembered one of these is make the length to be equal, why is that ?

TIA.

Added after 1 hours 15 minutes:

any suggestion ??

##### Full Member level 4
Sizing consideration depends upon mainly three
factors

1. Current value
2. Mismatch issues, random or systmatic
3. Scaling factor

Better to make lengths equal so that you will
have one variable fixed and you will have to
manupulate the widths only. Make sure that
you use typically equal widths and length
when the multiplying factor needed is 1
to provide better match.

### Julian18

Points: 2

#### yibinhsieh

##### Full Member level 4
For good current mismatch and good noise behavior, I usually use the following rules:

1.Use long channel device.
You can sweep the IV curve to decide which length is long channel device.

2.ajust the width to make it to operate in stauration region.

3.If the PSRR or CMRR are important, use cascoded architecture.

Best Regards,
Yibin.

#### gszczesz

##### Full Member level 2
Yet another take on current mirror sizing:

1) Determine your alowable mis-match given saturation. This determines the AREA.
For example, in one particular process the mismatch is 20mV/root(W*L). If you are looking for a 1-sigma of 2mV, then you will need a W*L=100.

2) Determine the minimum Vdsat you need to make the mis-match approximation true. The mis-match aprpoximation is done in saturation usually with a typical vdsat. This will determine the ratio of W/L.

3) Determine required Rout. If Rout is too small, make the L larger (keeping area constant). You'll be trading off minimum operating voltage for output impedance.

Now you never really want to go through all that in a typical design, so rule-of-thumbs are much easier. I use the following:

1) For a good Vdsat, I typically use 1uA per square. So if I want 10uA current source, for a W=10um, I will use L=1um. For a 20uA current source, for a W=10um I will use L=0.5um. To keep the area constant, I would use W=15um, L=0.66um.

The longer the device, the better the mismatch because the gain is reduced. A reduction in gain reduces Vth contribution to output current error. You are left mainly with lithografical. So if I don't need a low operating voltage on the current source, I'll try to make the current density even larger, like 2-5uA/square.

Greg

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V
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### Shishira

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#### mdcui

##### Advanced Member level 4
Greg really gives a very good explaination of the sizing method, and another thing to be careful in design current mirror is to avoid systematic device mismatch, for example, for a 1:2 ratioed current mirror there are two choices

a)source side W/L=10/1, mirror side single device W/L = 20/1
b)source side W/L=10/1, mirror side two device in parallel , both has W/L = 10/1

obviously option (b) is better considering the delt W and delta L caused by process. you can use spice to measure the effective L and W to understand this. use probe lv1(Mxxx) and lv2(Mxxxx)

### Julian18

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V
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#### pbs681

##### Full Member level 3
mdcui said:
Greg really gives a very good explaination of the sizing method, and another thing to be careful in design current mirror is to avoid systematic device mismatch, for example, for a 1:2 ratioed current mirror there are two choices

a)source side W/L=10/1, mirror side single device W/L = 20/1
b)source side W/L=10/1, mirror side two device in parallel , both has W/L = 10/1

obviously option (b) is better considering the delt W and delta L caused by process. you can use spice to measure the effective L and W to understand this. use probe lv1(Mxxx) and lv2(Mxxxx)
Could you explain why did you say that option b is better. I think option a is better when you want to minimise the delta L and W effect.. My reason is that relatively device with bigger size will have smaller effect...

#### gszczesz

##### Full Member level 2
Edge effects in an MOS can be significant contributor to threshold or ratio errors.

Firstly, the edge of an MOS is not a brick wall. It extends slightly out or in, and thus 10um width is not exactly 10um, but say 10.5um width. If you just double the width and the edge effects stay constant, then you'd be comparing 10.5um to 20.5um, not exactly a great ratio.

Secondly, other implants nearby can seep in and change your thresholds. I worked in a process where the stop-implant seeped in more then 7um to raise the threshold of the MOS. When MOS were not unit-sized, then the ratio's were horrible.

So for good matching, you absolutely have to have unit sized MOS. Unit sized MOS means all MOS's are groups of the same dimensions, so a 5:1 ratio would involve 5 parallel MOS on one side, and 1 MOS on the other.

In some companies they simply don't allow non-unit sized mirrors out of the designers. I don't believe in such harsh rules because there are situations where you don't care so much about accuracy but do care about area. But if matching is of concern, make sure everything is made from the same MOS.

As a side note, some places even demand from their engineers that the current goes in the same direction. They try to eliminate doping gradients from affecting matching. If you have a common centroid layout then the net gradient effect is averaged out, however, this assumes that every MOS in a given coordinate has the same Vt offset if replaced by another. The problem is that the MOS doesn't occupy a single point, but an area that has a gradient. Furthermore, the MOS is not symemtrical because it has a pinch-off region. This means that depending on what orientation the MOS has, the pinch off region will occupy a different doping intensity, and hence the average doping offset for the active channel is different. If on the other hand the MOS is in the linear region and there is no pinch-off, then you could consider it symetric and the average of the doping is the same regardless of the MOS orientation.

Points: 2

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### Shishira

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#### bambooer

##### Newbie level 1
Thanks for edaboard, really a onepiece for the designer

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