Single stage offline PFC'd flyback converter without ground-splitting current sense

[treez]

Hello,

The NCL30001 controller implements an offline PFC’d single stage flyback converter. This operates in fixed frequency, and is intended for CCM.
The schematic for it involves only a FET source sense resistor. It does not include a current sensing resistor in the return path. As you know, the source sense resistor signal represents the Flyback FET current , and this is not the actual total current.
As you know, virtually all PFC Boost converter controllers involve a sense resistor which is actually in the return path. This is , obviously because in order to make the input current follow the input voltage (sinusoidal), its obviously necessary to sense the actual input current. If its not sensed, then we cannot know what it is.
As such, the PFC operation of the NCL30001 will have significant limitations over varying line and load. Would you agree? I am wondering if they have implemented some fantastic algorithm in the NCL30001 which somehow overcomes this? I very much doubt it, because if they have, then its “goodnight Vienna” to all the PFC controllers which comprise a current sense resistor in the return path. –Obviously, such a sense resistor breaks up the ground…it “splits” the ground, which is something which is of some level of inconvenience. If controllers existed which obviated the need for such a “ground-splitting” sense resistor, then all such controllers would die off overnight….since they have obviously not all dies off, I put forward that the NCL30001 has a level of inflexibility in its PFC operation…would you agree?

Certainly, all the app notes suggest correctly PFC’d operation only over a 2:1 output voltage range.
NCL30001 datasheet:

www.onsemi.com/pub/Collateral/NCL30001-D.PDF

 

[CataM]

Nothing new so far. Review Buck PFC controllers and see that sensing the current in the transistor's source is usual. See e.g. NCL30002.

 

[Easy peasy]

In BCM with only FET source current sensing you can get 0.95 PF, some chips even increase the PWM a bit around the 0-30 deg & 30 deg - 0 to make it less steep sided just before after the zero crossing ...

 

[mtwieg]

I previously used the UCC28070, which also implements average CMC and CCM, but only senses switch current. In that case they have a special block which reconstructs the input current waveform while the switch is off. I don't know how the NCL30001 gets around the issue, and I don't see the datasheet even mentioning it.

Strangely, in their block diagram they show both the filtered and instantaneous switch current being fed into the PWM comparator...

 

[treez]

Thanks, the attached two simulations in ltspice show just why BCM operation for single stage flybacks is so terrible (..if the switching frequency is not limited)...the problem is, even if you do limit the switching frequency, the mains harmonics and power factor get worse.

The attached Single stage offline PFC’d BCM flyback simulations in LTspice show just why Boundary conduction mode is so terrible for single stage PFC solutions if the switching frequency is not limited.
At 60W, the switching frequency inside a single 10ms half sine ranges from 65khz to 190khz.
This is really wider than liked, but is something you have to accept with BCM operation.
At 25W, the same stage has its switching frequency ranging from 145khz to 350khz….this is far too high frequency for an offline flyback.
I am sure you agree that unless a BCM flyback PFC stage is limited in its upper frequency level, then it is not a viable solution. The problem is, none of the offtheshelf single stage flyback PFC chips show any evidence of switching frequency limitation in their datasheets. Do you know why this is?
The limitation of switching frequency can be done by having a minimum off time. However, eg the L6562 datasheet shows no such limitations.
Do you know why?

L6562 datasheet:
https://www.google.co.uk/url?sa=t&r...et/l6562.pdf&usg=AOvVaw3Wr6KcQFud0TVMTNZLDEA6

 

[mtwieg]

You're not making a convincing argument if you don't explain how those numbers and PWL files were derived. The shape of the line current doesn't look like it's being controlled properly in the first place.

 

[treez]

Thanks, its BCM operation over the whole 10ms half cycle...and it just has a constant on time throughout.
But you are right.......
With a boost pfc, such a modus operandi gives a perfect sine mains input current.
With a flyback it does not...but its good enough to pass pfc and mains harmonics regs.

However, with the flyback, when it starts going lighter load, and the controller say starts operating more deeply into dcm due to a min off time constraint, then the mains harmonics start failing.