it is entirely possible the FIFO is implemented with flops that have async reset themselves. if they are async, they are async to any clock. the FIFO could have 3 clocks, 10 clocks, it wouldn't matter.
should the clocks be gated so they will start after de-assertion of the reset in order to eliminate the metability?
As for as I know, using the async reset may bring to the logical errors ... So, how to use the async reset on the safe side? stop the clocks during the reset?
should the clocks be gated so they will start after de-assertion of the reset in order to eliminate the metability?
As for as I know, using the async reset may bring to the logical errors ... So, how to use the async reset on the safe side? stop the clocks during the reset?
"properly designed flip flop can do this for you" - the timing of clock and reset is defined externally to the flop... so how could it handle internally? the clock & reset can rise/fall close one to another, so removal/recovery violations may happen.
What is crosscheck? could you explain, please?
I can choose the flops type ... For FIFO itself I have chosen FlipFlops without reset. As for the around logic - FlipFlops with the reset. But there is only one reset pin but two clock domains... So, if I want to synchronize the reset, so for which clock domain? write side? read side? slowest clock? fastest clock? provide it asynchronous to two clock domains?
Have you checked with the vendor to see if the FIFO locally synchronizes the asynchronous reset input to both clock domains internally?
The last time I worked on an ASIC (10+ years ago) the dual clock FIFO we used only had a single asynchronous reset and that reset was synchronized to both clock domains in the FIFO core.
I've also seen this done on FIFO cores from FPGA vendors.