Single Port RAM Verilog.. HELP!!

[mehra_pallavi]

Totally new to verilog, working on a HW project where I'd have to design a single port ram that is 8 bits wide and has 16 memory locations. The description is as below;

Write RTL description and testbench for the Single Port RAM, which is 8 bit wide and has 16
memory locations. The data can be written on a memory location by providing its address and
making “we” high and “oe” low. The data can be read from a memory location by providing the
address and making “oe” high and “we” low. This RAM has single port for data writing and reading.

GivenRTL

module ram(data,
we,
enable,
addr);

input we,
enable;
input [3:0] addr;
inout [7:0] data;
// Step 1. Declare a 8 bit wide memory having 16 locations.


// Step 2. the logic for writing data into a memory location
always@(data,we,enable,addr)
if (we && !enable)
mem[addr]=data;

// Step 3. the logic of reading data from a memory location
assign data= (enable && !we) ? mem[addr] : 8'hzz;
endmodule


Given Testbench

module ram_tb;
wire [7:0] data;
reg [3:0] addr;
reg we,enable;
reg [7:0] tempd;

integer l;

// Step 1. Instantiate the RAM module and connect the ports

assign data=(we && !enable) ? tempd : 8'hzz;

task initialize();
begin
we=1'b0; enable=1'b0; tempd=8'h00;
end
endtask

// Step 2. Write a task named "stimulus" to assign data into
// "addr" and "tempd" inputs through i and j variables


// Step 3. Understand the various tasks used in this testbench
task write();
begin
we=1'b1;
enable=1'b0;
end
endtask

task read();
begin
we=1'b0;
enable=1'b1;
end
endtask

task delay;
begin
#10;
end
endtask

initial
begin
initialize;
delay;
write;
for(l=0;l<16;l=l+1)
begin
stimulus(l,l);
delay;
end
initialize;
delay;
read;
for(l=0;l<16;l=l+1)
begin
stimulus(l,l);
delay;
end
delay;
$finish;
end
endmodule

Would really appreciate if anybody could help with the RTL description and the test bench.

Thanks in advance