Importantly, is the Y-axis right? I mean you have a Y axis which calls of degrees. I do not think so. I do not think that there is an opamp which will cause a 5 degree phase shift.
Secondly, have you put the options as .OPTIONS UNWRAP for the phase plot? If you have done so, then the cause is due to two RHP zeroes and not multiple poles. The problem in the design could be due to the sizing of the cascode transistors which are at the current folding end. So, kindly verify them.
Also, have you used the positive input for testing the amp because there is no phase shift at DC. Are you doing a open loop test? If that is the case, you are actually looking for a lot of phase margin(which I think is next to impossible at those frequencies).
Kindly clarify me on these things.