single nmos lvs - four "missing port " errors

[Ian.Y.Jin]

single nmos lvs

Dear All,

I'm currently working on a single transistor layout. The transistor has four pins in the schematic (namely, gate, source, drain and bulk). In the layout, I define four pins accordingly, using 'pin' layer for both pins and labels. But after LVS, none of the pins are recognized, and I have four ** missing port ** errors. Anybody has encountered same problem? Thanks.


Best Regards,
Ian Jin

 

[erikl]

single nmos lvs

Did the layout extraction work correctly?

 

[Ian.Y.Jin]

Re: single nmos lvs

Thanks for the tip. Unfortunately, currently I'm working with an immature designkit, no extraction tool available yet. Any other way to look around this problem?

An interesting observation is that, once I put this transistor in a higher-level circuit (e.g., a cascode stage), th LVS for the single transistor part is without errors, but with two warnings:
1. Extra ports in source (i.e., Gate);
2. Ambiguity points were found and resolved arbitrarily (i.e., ambiguity about 1 net).

Does this ring a bell for you? Thanks.


Best Regards,
Ian Jin

 

[erikl]

single nmos lvs

AFAIK LVS without extraction doesn't work correctly.

 

[Ian.Y.Jin]

Re: single nmos lvs

Hi,

It turned out that for the designkit I'm currently using, the 'pintext' (instead of 'pin') layer should be used for the pin definition. After the changes, the lvs is clean.


Cheers,
Ian Jin

 

[erikl]

single nmos lvs

Thanks for your feedback! So it works without extraction; this was unknown to me: I always had to extract before LVS. Congratulations!
Cheers, erikl