single-ended to differential converter design

[slchen]

Dear All:

I am doing the DLL design.
My delay line is differential type, and however the input clock of the DLL is single-ended.
So, I need a single-ended to differential converter.
I use two inverters cascaded to generate the in-phase clock (CK) and use a inverter and a transmission gate cascaded to generate out-of-phase clock (CKB), as shown in the atatched figure.
But, the two output signals (CK and CKB) have skewso that the delay line can't work correctly.

Can you give me some comments on the s-to-d design?
Or how to solve this issue?

Thanks a lot.
slchen



Another question!!!
My DLL structure is regulated-VDD type, like S. Sidiropoulos' paper (Symp. VLSI circuits, 2000).
Is the differential-type VCDL necessary?
Or only use single-ended VCDL is enough ?

slchen

 

[jfyan]

Dear All:

I am doing the DLL design.
My delay line is differential type, and however the input clock of the DLL is single-ended.
So, I need a single-ended to differential converter.
I use two inverters cascaded to generate the in-phase clock (CK) and use a inverter and a transmission gate cascaded to generate out-of-phase clock (CKB), as shown in the atatched figure.
But, the two output signals (CK and CKB) have skewso that the delay line can't work correctly.

Can you give me some comments on the s-to-d design?
Or how to solve this issue?

Thanks a lot.
slchen




Another question!!!
My DLL structure is regulated-VDD type, like S. Sidiropoulos' paper (Symp. VLSI circuits, 2000).
Is the differential-type VCDL necessary?
Or only use single-ended VCDL is enough ?

slchen

hi slchen,
maybe you can add more inverters before or after the cmos pass-gate, of course, to match the signal, its counterpart also needed.
differential-type VCDL has much higher psrr compared with single -ended one, but more power and device noise.
jeff