jayanth.neo
Junior Member level 1
folded cascode design
Hi all,
I am new to analog design and I am currently designing an Nmos input folded cascode amplifier. I have the following specs to meet at Vdd 2.7V and 0.35u technology:
can use an ideal current source of 5uA which can be mirrored accordingly.
Aol >50dB
swing = 2 V
power dissipation = 0.8mW.
Load cap = 15pF
UGF - 25MHz
Phase margin = 60
HD3 of 50dB with 5Khz input signal.
I would like to know how to start with the sizing of the cascode stack consisting of 2 PMOS and 2 NMOS on each branch. I am designing for a single ended output ( and have diode connected an NMOS on one side of the branch.
What imp points should I consider while sizing the Diff pair and the cascode stack for a UGF > 25MHz and phase margin of 60?
What can be the length of the transistors? I am currently using 1um for all transistors at .35um technology.
Any suggestion on the design procedure and useful directions will be greatly helpful.
Thanks
Hi all,
I am new to analog design and I am currently designing an Nmos input folded cascode amplifier. I have the following specs to meet at Vdd 2.7V and 0.35u technology:
can use an ideal current source of 5uA which can be mirrored accordingly.
Aol >50dB
swing = 2 V
power dissipation = 0.8mW.
Load cap = 15pF
UGF - 25MHz
Phase margin = 60
HD3 of 50dB with 5Khz input signal.
I would like to know how to start with the sizing of the cascode stack consisting of 2 PMOS and 2 NMOS on each branch. I am designing for a single ended output ( and have diode connected an NMOS on one side of the branch.
What imp points should I consider while sizing the Diff pair and the cascode stack for a UGF > 25MHz and phase margin of 60?
What can be the length of the transistors? I am currently using 1um for all transistors at .35um technology.
Any suggestion on the design procedure and useful directions will be greatly helpful.
Thanks