yes dc voltage steady, I'm using two indictor in both side of dc in series with 1.mf cap in parallel, also used 33nf cap from both ac output to ground of 320Is the DC voltage still steady 310-315 Vdc when you increase the load? Is there a filter on the full bridge output?
thanks tsan500
I have not feedback or reference to generated spwm signal, so I asked if sinewave inverter need feedback from H-bridge to recalculate signal value according to feedback voltage?
What do you mean duty cycle in 90 degree? Usually modulation index is used to describe the ratio of amplitude of sine reference vs. amplitude of carrier. On your case, peak of the sine reference should equal peak of the carrier. It is possible, that now amplitude of the sine ref samples are too low, therefore producing lower output voltage.
I calculated quickly on excel and got close the same values for sine ref table. Last value of 240 means that amplitude of the generated wave is 240/255 of the amplitude that would result when the last value is 255. You can compensate for it by increasing the DC voltage. Also other losses can be compensated by increasing DC voltage. If losses are too high, then change the components or circuit.I used this lookup table 0, 13, 26, 39, 52, 64, 77, 89, 101, 112, 124, 135, 145, 155, 165, 174, 183, 191, 199, 206, 212, 218, 223, 227, 231, 234, 237, 239, 240
it's from 0 to degree 90 of sine signal , each value will repeat 3 times
as you see last value is 240 , and timer in uC totally overflow in 255 ,I can't increase this value because uC need processing time,
it's about 94% of duty cycle of the highest value, so I think there isn't problem in software
To avoid bootstrap circuit failure, bootstrap capacitor can be made bigger than basic calculation using carrier frequency gives. The reference is sine wave so it will be on maximum only limited time. Limiting duty cycle and having higher DC voltage seems better option, though.Hi,
Duty cycle:
If dury cycle is less than 100% then you never can get full peak output voltage = bus voltage.
If duty cycle is 100% then your driving circuit (depending on what circuit you use) may fail because of bootstrap circuit failure.
There will be voltage drop....in capacitors, traces, switching circuit, filters....
Klaus
Me too.I calculated quickly on excel and got close the same values for sine ref table.
You are correct. I merely compared amplitude values. I checked the numbers and plotted the samples over half cycle but the problem does not appear with half cycle. The issue comes when only 90 degrees of the cycle are used. I have used on my project full cycle which made table indexing really easy but perhaps here there is only very limited memory. I made a picture showing principle of 90 degrees sampling I think would work. It is only for 5 samples for 90 degrees to show the principle. The 90 degrees sample is used only once per half cycle.Hi,
Me too.
I found out (or at least it seems so) your last item is not 90°, but 86.9°.
With 29 items per 90°, so step sizte is about 3.10°.
I wonder why the 90° is missing. For 29 items per 90° you need 30 items in total.
But maybe I´m wrong.
Klaus
I think I'm in finishing of 80% of my inverter, the problem here is with no load I got square wave form , is this normal?
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