Sine wave generation using Direct Digital Synthesizer in xilinx ISE

[Drastic]

Please help me out in resolving the issue with sine wave generation using DDS. How to generate 4 different sinusoidal signals with phase angles 0,90,180 and 270. How phase increment values are related to frequency. am designing my QPSK modulator for a clock frequency of 100 MHz. IP core has been generated for DDS, hw to make it work efficiently for sine generation. Do help me in sorting this problem. Thanks in advance

 

[KlausST]

Hi,

what output frequency range and resolution do you need? This is the most important information to setup your DDS.

Usually a fixed counter increments phase angle steps. Then from a lookup table you find the sine values to the angle value.
The increment value is proportional to your output frequency.

if the increment value is 1 degree with 100MHz, then output frequency fo = 100MHz * 1degree / 360degree = about 300kHz

But the increment value could be 0.000001degree, then output frequency is about 0.3Hz

Klaus

 

[Drastic]

Thanks for u help. My design parameters are as following, output frequency is 25mhz and frequency resolution is found to be 1525. The phase increment to the DDS is found to be 1111111111111111. How to relate this with that of output freq and phase angle ?

 

[FvM]

You don't need DDS to generate a 25 MHz signal with 100 MHz clock, because the out is simply a sequence 0,+1,0,-1. A few flip-flops can generate it.