module sine_cos(clk, reset, en, sine, cos);
input clk, reset, en;
output [7:0] sine,cos;
reg [7:0] sine_r, cos_r;
assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};
assign cos = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};
always@(posedge clk or negedge reset)
begin
if (!reset) begin
sine_r <= 0;
cos_r <= 120;
end else begin
if (en) begin
sine_r <= sine;
cos_r <= cos;
end
end
end
endmodule // sine_cos
module pwm_gen(clk,reset_n, pwm_din, pwm_out);
input clk, reset_n;
input [7:0] pwm_din;
output pwm_out;
reg pwm_out;
reg [7:0] pwm_cnt;
assign pwm_out_nx = (pwm_cnt <= pwm_din) ? 1'b1 : 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
pwm_cnt <= 0;
pwm_out <= 0;
end else begin
pwm_cnt <= pwm_cnt + 1'b1;
pwm_out <= pwm_out_nx;
end
end
endmodule
module sine_cos_tst();
reg clk, reset;
wire [7:0] sine,cos;
wire clk_256, pwm_out;
reg clk_256_r;
reg [7:0] cnt_256;
sine_cos u1(clk, reset, clk_256, sine, cos);
pwm_gen pwm_gen (clk, reset, {~sine[7],sine[6:0]}, pwm_out);
initial begin
$shm_open("./WAVEFORM");
$shm_probe(sine_cos_tst, "AS");
clk = 0;
reset = 0;
cnt_256 = 0;
clk_256_r = 1'b0;
#33 reset = 1;
#2000000 $finish;
end
always #5 clk = ~clk;
always @ (posedge clk) begin
cnt_256 <= cnt_256 + 1;
clk_256_r <= cnt_256[7];
end
assign clk_256 = cnt_256[7] & ~clk_256_r;
endmodule
Usman Hai said:Is it possible to generate some sort of sine wave generation on FPGA.
Using CORDIC algo is it possible.
what shud we do if we want to generate analog signal on FPGA.
is there any alternative.
USMAN HAI
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