'sine' remains a black box since it has no binding entity (in test bench)

[sangitacp93]

Hey,

The simulation gives a warning error of "
[VRFC 10-4940] 'sine' remains a black box since it has no binding entity ["C:/Users/L/.../L.srcs/sim_1/new/L_tb.vhd":35]"

So at simulation output also has 'U' value.

I am using Vivado 2019.2, library is set to 'work' , file type is 'VHDL' and it is used for both 'simulation' and 'synthesis'.

What am I missing in the test bench or any setting ??

Thank you in advance. I appreciate.

 

[dpaul]

Recheck whether all design/test sub-modules have been added to your project before running simulation.