buenos
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xe version supports only a single hdl
hi.
in my project, i used IP cores from opencores.org .
I had 2 choices:
-synthesize the cores separatelly, and copy the result netlist to my project folder.
Problem: then in simulation, all the signals coming from the IPs are "UUUUUUUU"
-synthesize them together, in a single ISE project.
Problem: i get this message: "XE version supports only a single HDL". i think its because the different IPs are in 2 languages: VHDL and Verilog.
so, how to simulate the whole project? I want to check internal signals between the IPs. separatelly i simulated tehm, they worked, but on the target, they dont.
hi.
in my project, i used IP cores from opencores.org .
I had 2 choices:
-synthesize the cores separatelly, and copy the result netlist to my project folder.
Problem: then in simulation, all the signals coming from the IPs are "UUUUUUUU"
-synthesize them together, in a single ISE project.
Problem: i get this message: "XE version supports only a single HDL". i think its because the different IPs are in 2 languages: VHDL and Verilog.
so, how to simulate the whole project? I want to check internal signals between the IPs. separatelly i simulated tehm, they worked, but on the target, they dont.