#### Zeppelin1007

##### Newbie level 2

Im pulling my hair out over this one..

I was assigned to create a simple repeat adder. InputA is added to itself a number of InputB times. Works fantastically in simulation. WHen it hits the board however, the outputs i get have a "3" added to the output on the left side.

For example:

if i input InputA= 0101 and inputB = 0100, my output should be 01000101. Ok.

Load+clock = Display Inputs A and B on the LEDs. This doesnt exactly happen. Instead i get 00110101....in fact, no matter what i put in, the "B" side, ALWAYS has 0011...

So if i begin addition, enable = high + Clock, I should get 00000101, then 000001010, 00001111...NOPE, i get 00111010...00111111

Can somebody point out where this magical number is coming from? Im using XIlinx ISE 14.1. I do get the warning that InputB has no load, PAR will not attempt to route this signal. Is it because im routing my inputs to variables?

Code:

```
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity muladder is
port(
klok: in std_logic;
load: in std_logic:='0';
InputA: in std_logic_vector(7 downto 0):="00000000"; --Preset states to nothing is "undefined"
InputB: in std_logic_vector(3 downto 0):="0000";
enable: in std_logic:='0';
Output: out std_logic_Vector(7 downto 0):="00000000"
);
end muladder;
architecture multiplier of muladder is
Begin
process (klok, load, enable)
Variable Temp, Adda: std_logic_vector(7 downto 0):="00000000"; --Used variables to update them
Variable InputBSub: std_logic_vector(3 downto 0):="0000";
begin
if (rising_edge(klok)) then
if load = '1' and enable = '0' then
Temp:= InputA; --loads Input A
Adda:=InputA; --Loads input A to be added to itself
InputBSub:= InputB; --THe counter variable
Output(3 downto 0)<= Temp(3 downto 0); --Supposed to output InputA showing its been loaded
Output(7 downto 4)<= InputBSub; -- Supposed to output InputB showing its been loaded
elsif (load = '0' and enable = '1') then
Temp:= Temp+AddA;
InputBSub:= InputBSub - 1;
end if;
Output<= Temp;
end if;
end process;
end multiplier;
```

I know im not the best VHDL coder. As you can probably tell im more of a C++ guy. But im giving it a shot. I just cant figure out where this extra 2 bits are coming from. I should mention that if A= 0, and B = 0, i still get 00110000. if i enable and pulse the clock, it begins to count by 3, going 00110000, 01100000, so on and so fourth. My output is supposed to be 8 bit, with leftmost being MSB. yet it looks like the output is still split? despite giving it an 8 bit output.

Im kicking around the idea my board is screwed up? its the xilinx spartan 6, but some other projects run fine on it...ALU, Shift register...i say this because i have another version of the same program, although done long hang addition/subtraction using bitwise XOR/OR/AND...and guess what? SAME RESULT! So im guessing something in my if/then handling?

Thanks in advance guys. Im really puzzled on this one and i'd really like to understand why im getting what im getting.