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Simulation Warnings in agilent ads

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dpa2007

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Hello everyone,
i currently simulate a digital block diagram model in ADS and i get these warnigs:
Number of nodes with only one device attached (topology corrected): 25
Number of nodes with no DC path to ground (topology corrected): 8
but i don't have any "floating pin" in my circuit.
could anyone help me, figure out the simulation problem?
thanks in advanced.
 
Hello,thank you for your reply.
here is my netlist and log file
 

Attachments

  • netlist.txt
    20.4 KB · Views: 301

Warning detected by hpeesofsim in topology check during circuit set up.
The following nodes have only one device attached to them (topology corrected):
D4.B1._net17
D4.L4._net46
D4._net292
D4.Q2._net40
_net548
D3.D6._net35
D3.S3._net59
D3.S3._net60
D3.D3._net46
D3.L5._net326
D3.L5._net327
D3.L5._net328
D3.L5._net322
D3.L5._net320
D3.L5._net318
D3.L5._net315
D3.L5._net312
D3.L5._net311
D3.M1._net44
_net540
B3._net17
D2._net22
G2._net35
B1._net17
D1._net46
The following nodes have no DC path to ground (topology corrected):
D3.L5._net326
D3.L5._net327
D3.L5._net328
D3.L5._net322
D3.L5._net320
D3.L5._net318
D3.L5._net312
D3.L5._net311

I think there is no problem since they are internal nodes in provided model which we can't access except for "_net548" and "_net540".
"_net548" and "_net540" are connected to "Open Circuit Type OutSelector".

DBPSK_Mod:D4 _net552 _net554 RIn=50 Ohm ROut=50 Ohm RTemp=274 FCarrier=1000000 Hz SymbolTime=3.7037037 sec Power=0.01 W ExcessBw=0.5

DBPSK_Demod:D3 _net548 _net547 RIn=50 Ohm ROut=50 Ohm RTemp=274 RefFreq=100000 Hz SymbolTime=0.001 sec ExcessBw=0.5

OutSelector:O1 _net540 _net548 OutFreq=100000.0 Hz

BinaryCoder:B3 _net536 _net552 RIn=50 Ohm ROut=50 Ohm RTemp=274 SymbolTime=3.7037037 sec Type=0

Data:D2 _net536 ROut=50 Ohm RTemp=274 TStep=Tstep usec BitTime=SymbolTime usec UserPattern="" Type=1 SequencePattern=8 Repeat=1

GainRF:G2 _net527 _net518 RIn=50 Ohm ROut=50 Ohm RTemp=274 Gain=0.2+j*0.0 NoiseFigure=6 GCType=3 TOIout=dbmtow(37) dBc1out=dbmtow(27) PSat=1 W GCSat=1 GComp="0.0.0.0.0.0"

BinaryCoder:B1 _net547 _net517 RIn=50 Ohm ROut=50 Ohm RTemp=274 SymbolTime=3.7037037 sec Type=0

DelayRF:D1 _net536 _net515 RIn=50 Ohm ROut=50 Ohm RTemp=274 Delay=17.5 usec InterpolationMethod=0 IncludeCarrierPhaseShift=1
 
Last edited:

thank you very much for the answer.i just saw your reply post.so there is no need to worry about these warnings?
 

Yes, you don't have to worry about them at all.

my problem was that i was able to implement and simulate simple (or more advanced) circuits and block diagrams but that one was (still is...) a bigger trouble.
thanks again.
 

i made some changes in the design.
i don't get any warnings.
but i get an error:
Redefinition of `LOpower_dBm'
is this error telling me that this variable is defined more than one times?
 

hello i am attaching the netlist.
is better to provide the design?
or is it equivalent?:?:
thanks in advanced.
 

Attachments

  • netlist1.txt
    6.3 KB · Views: 94

hello i am attaching the netlist.
This is not ADS Format Netlist.
This is SPICE Format Netlist.

Why do you show SPICE Format Netlist ?

Simply "LOpower_dBm" is defined at two places. And they are not pass parameters of Subcircuit.
.subckt SDC_AMFA_Cosim P1 P2
.param LOpower_dBm=7
.param LO_Freq=2.312GHz
.param RF_Freq=2.4GHz
.param RFpower_dBm='-50'

xDown_Converter P1 P2 _net12 SDC_AMFA Filt_Freq=88meg
RR3 _net12 _net4 50
.ends SDC_AMFA_Cosim

.subckt SUC_AMUFA_Cosim P1 P2
.param LOpower_dBm=7
.param LO_Freq=2.312GHz
.param IF_Freq=88meg
.param IFpower_dBm='-50'

RR3 _net13 _net4 50
xUp_Converter P1 P2 _net13 SUC_AMUFA Filt_Freq=2400meg
.ends SUC_AMUFA_Cosim

Your problem is very trivial.
I can find duplicate or unnecessary parameter's definitions other than "LOpower_dBm" in your netlist.
Carefully check all your schematics.
 
Last edited:

i am a new user.
sorry for the spice netlist.
how can i find the ads netlist?
i'm going to delete the duplicate entries.

edit:
i found how to get the ads netlist
 

Last edited:

you're right,
i believe this one is the correct one.

i made some other changes(replace the one converter) and now i am getting errors for the Tstep and other time parameters which i had change also.
so i believe i must correct them.
i also used transient analysis in cosim blocks and not the envelope, which is now deactivated.
 

Attachments

  • netlist.cnex.txt
    6.1 KB · Views: 73
Last edited:

you're right,
i believe this one is the correct one.
Not correct at all.
Attached "netlist.cnex.txt" is a SPICE Format Netlist.
Surely read contents of link in my append.


i made some other changes(replace the one converter)
and now i am getting errors for the Tstep and other time parameters which i had change also.
so i believe i must correct them.
i also used transient analysis in cosim blocks and not the envelope,
which is now deactivated.
What on earth do you want to mean ?
Have your all problems been able to resolved ?
 
Last edited:

Not correct at all.
Attached "netlist.cnex.txt" is a SPICE Format Netlist.
Surely read contents of link in my append.


What on earth do you want to mean ?
Have your all problems been able to resolved ?

hello pancho,thanks again for helping.

in my design i had to used an upconverter and a downconverter.
when i used the component SDC_AMFA and SDC_AMUFA as cosimulation for up and down converters i get the error message with the dublicate variable:LOpower_dBm.
when i used only the SDC_AMFA this error eliminated and i get errors about the timings like TStep.

i get the netlist_new.txt,that i am currently attached, from the netlist.log file in project folder.is this the correct and not the other from menu:
Tools>Netlist Export>Create ADS FrontEnd Netlist?
 

Attachments

  • netlist_new.txt
    18.2 KB · Views: 82

What is your native language ?
It is very difficult and tired to read and understand your poor sentences.

Surely read documents.

Tools>Netlist Export>Create ADS FrontEnd Netlist?
This is a SPICE Format Netlist.
Again surely read documents.

i get the error message with the dublicate variable:LOpower_dBm.
when i used only the SDC_AMFA this error eliminated and i get errors about the timings like TStep.
Your problems are very easy and trivial.

You use "global parameter definition" in your schematics.
Do you understand this ?
Carefully check all schematics.
 
Last edited:

What makes you think that netlist_new.txt from post #13 is a SPICE netlist?
It is ADS Format Netlist.

You can't understand a meaning of my append.
Surely read my append of "#14" as reply for "#13".
Tools>Netlist Export>Create ADS FrontEnd Netlist?
This command is for netlisting a SPICE Format Netlist.

Many people wrongly use this command for netlisting ADS Format Netlists.
See The Designer's Guide Community Forum - ADS2009 Harmonic Balance.
 

Again surely read my append in "#14".

No. I just wanted to tell you to read the questions and look at the file before posting answers what the file is.
Of course, I looked file. So I can write following in "#14".
If I don't see "netlist_new.txt‎", I can't know that global parameter definition" is used.
You use "global parameter definition" in your schematics.
Do you understand this ?

Rather I tell you surely to read all appends and not to append valueless comments.
I don't mention "netlist_new.txt‎" in "#14" at all.

I explained "Tools>Netlist Export>Create ADS FrontEnd Netlist" is for SPICE Format Netlisting not ADS Format Netlisting.
 
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thank you again for the advice Pancho,
i am going to read again,more carefully the links.
sorry for the unwanted information that i posted.

---------- Post added at 17:00 ---------- Previous post was at 16:51 ----------

What is your native language ?
It is very difficult and tired to read and understand your poor sentences.

Surely read documents.

This is a SPICE Format Netlist.
Again surely read documents.

Your problems are very easy and trivial.

You use "global parameter definition" in your schematics.
Do you understand this ?
Carefully check all schematics.

Hello Pancho,thanks again.
yes i can understand you are telling me.
but i am a new user in ads a not very familiar with simulations with analog and digital parts.
I'm going to check again all schematics.
 

Last edited:

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