waqar86
Junior Member level 2
i have a transmitter(upto 1 megabaud) and a receiver(0.1 Megabaud - 1 MegaBaud) where i have to avoid the link going down between transmitter and receiver when the transmitter isn't sending data. So i thought of a scheme with state machines i-e,
Transmitter Side,
when data_in = 0 then sequence 10 is sent to receiver in two states(i-e 2 clk cycles)
when data_in = 1 then sequence 01 is sent to receiver in two states(i-e 2 clk cycles)
when data_in = x then sequence 11 is sent to receiver in two states(i-e 2 clk cycles)
Receiver Side,
when 10 is received(means data_in=0) from transmitter, it is sampled in 4 clock cycles as 1 1 0 0
when 01 is received(means data_in=1) from transmitter, it is sampled in 4 clock cycles as 0 0 1 1
when 11 is received(means data_in=x) from transmitter, it is sampled in 4 clock cycles as 1 1 1 1
Everything runs fine with simulation, but when i test it with function generator i don't get correct output, i think i am unable to synchronize data_in correctly with the code or may be i am missing some cases of data_in or may be its problem with the clock. If anyone can guide me a bit it will be highly appreciated.
Tranmitter Code
Receiver Code:
Top_Module:
Transmitter Side,
when data_in = 0 then sequence 10 is sent to receiver in two states(i-e 2 clk cycles)
when data_in = 1 then sequence 01 is sent to receiver in two states(i-e 2 clk cycles)
when data_in = x then sequence 11 is sent to receiver in two states(i-e 2 clk cycles)
Receiver Side,
when 10 is received(means data_in=0) from transmitter, it is sampled in 4 clock cycles as 1 1 0 0
when 01 is received(means data_in=1) from transmitter, it is sampled in 4 clock cycles as 0 0 1 1
when 11 is received(means data_in=x) from transmitter, it is sampled in 4 clock cycles as 1 1 1 1
Everything runs fine with simulation, but when i test it with function generator i don't get correct output, i think i am unable to synchronize data_in correctly with the code or may be i am missing some cases of data_in or may be its problem with the clock. If anyone can guide me a bit it will be highly appreciated.
Tranmitter Code
Code:
entity transmitter is
port(
data_in :in std_logic;
CLK :in std_logic;
output_to_fibre :out std_logic
-- final_output :out std_logic
);
end transmitter;
architecture Behavioral of transmitter is
--signal CLK_REC :std_logic;
signal NEWCLK_HALF :std_logic;
--signal output_to_fibre :std_logic;
type state_type_tx is (state1, state2);
signal next_state_tx: state_type_tx;
begin
clk_half:PROCESS(CLK)
VARIABLE COUNT:INTEGER:=0;
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNT:=COUNT+1;
IF COUNT<=10 THEN
NEWCLK_HALF<= '1';
ELSif COUNT>10 and COUNT<20 then
NEWCLK_HALF<= '0';
elsif COUNT=20 then
COUNT:=0;
END IF;
END IF;
END PROCESS clk_half;
TX_logic:process(NEWCLK_HALF)
variable i : integer :=0;
--variable start: integer:=0;
begin
if (NEWCLK_HALF'event and NEWCLK_HALF='1') then
case next_state_tx is
when state1 =>
if data_in ='0' then
next_state_tx <= state2;
output_to_fibre <= '1';
elsif data_in ='1' then
next_state_tx <= state2;
output_to_fibre<= '0';
else
next_state_tx <= state2;
output_to_fibre<= '1';
end if;
when state2 =>
if data_in ='0' then
next_state_tx <= state1;
output_to_fibre <= '0';
elsif data_in ='1' then
next_state_tx <= state1;
output_to_fibre<= '1';
else
next_state_tx <= state1;
output_to_fibre<= '1';
end if;
end case;
end if;
end process TX_logic;
end Behavioral;Receiver Code:
Code:
entity receiver is
port(
CLK :in std_logic;
input_to_receiver :in std_logic;
final_output :out std_logic
);
end receiver;
architecture Behavioral of receiver is
signal CLK_REC :std_logic;
type state_type_rx is (initial_state, one_state1, one_state2, one_state3, z_state1, z_state2, z_state3, state_carrier_rx);
signal next_state_rx: state_type_rx;
begin
clk_2:PROCESS(CLK)
VARIABLE COUNT:INTEGER:=0;
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNT:=COUNT+1;
IF COUNT<=5 THEN
CLK_REC<= '0';
ELSif COUNT>5 and COUNT<10 then
CLK_REC<= '1';
elsif count=10 then
COUNT:=0;
END IF;
END IF;
END PROCESS clk_2;
RX_logic:process(CLK_REC)
variable i : integer :=0;
--variable start: integer:=0;
begin
if (CLK_REC'event and CLK_REC='1') then
case next_state_rx is
when initial_state =>
if input_to_receiver='0' then
next_state_rx <= one_state1;
final_output <= '1';
elsif input_to_receiver ='1' then
next_state_rx <= z_state1;
final_output <= '0';
end if;
when one_state1 =>
if input_to_receiver='0' then
next_state_rx <= one_state2;
final_output <= '1';
end if;
when one_state2 =>
if input_to_receiver='1' then
next_state_rx <= one_state3;
final_output <= '1';
end if;
when one_state3 =>
if input_to_receiver='1' then
next_state_rx <= initial_state;
final_output <= '1';
end if;
when z_state1 =>
if input_to_receiver ='1' then
next_state_rx <= z_state2;
final_output <= '0';
end if;
when z_state2 =>
if input_to_receiver ='0' then
next_state_rx <= z_state3;
final_output <= '0';
elsif input_to_receiver = '1' then
next_state_rx <= state_carrier_rx;
final_output<= 'Z';
end if;
when z_state3 =>
if input_to_receiver='0' then
next_state_rx <= initial_state;
final_output <= '0';
end if;
when state_carrier_rx =>
if input_to_receiver ='1' then
next_state_rx <= initial_state;
final_output <= 'Z';
end if;
end case;
end if;
end process RX_logic;
end Behavioral;Top_Module:
Code:
ENTITY top_module IS
port (
data_in : in std_logic;
CLK : IN std_logic;
output_to_fibre : OUT std_logic;
input_to_receiver :in std_logic;
final_output :out std_logic
);
END top_module;
ARCHITECTURE behavior OF top_module IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT transmitter
PORT(
data_in : IN std_logic;
CLK : IN std_logic;
output_to_fibre : OUT std_logic
);
END COMPONENT;
COMPONENT receiver is
port(
CLK :in std_logic;
input_to_receiver :in std_logic;
final_output :out std_logic
);
END COMPONENT;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: transmitter PORT MAP (
data_in => data_in,
CLK => CLK,
output_to_fibre => output_to_fibre
);
uut2: receiver PORT MAP (
CLK =>CLK,
input_to_receiver => input_to_receiver,
final_output => final_output
);
END;