Hi,
I am new to this vhdl language.
I am doing structural style of asynchronous(mod 17) counter in vhdl.
I am using xilinx ise .During synthesis no errors were observed.
But in simulation all flip flop outputs are showing 'x;
What might be the wrong thing i am doing.
Help me in this.
i applied all the initial conditions .
Its waveforms are like earlier i.e xxxxx.
One funny thing is ,if i put flipflop outputs(q4,q3,q2,q1,q0) as inout signals and initilalize them at port declaration ,everything is working fine.
But the same is not coming if i declare them as signals and then initialize.
I remember, that missing initialization actually gives "uuu" values while "xxx" refers to incorrect designed logic or timing issues. I previously overlooked the term "asynchronous". Does it mean, you have a counter without a edge sensitive process? This in fact won't be synthesizable.
i am sending my code.
it is getting synthesized and showing results as uuuuu.
i tried by giving initialization value to reset signal s1.
But simulation result is uuuuu.
Earlier because of setting problem it is showing xxxxx[i.e instead of VHDL ,verlog was selected in the properties settings].
i am using ISE9.1.