simulation question on verilog

[V]

Hello friends,

in my behavioral code of state machine, its required to detect the input as low for N no if times. I am calling a task at that instance.

// Here I want to go to IDLE state after detecting low for N no of times


Receive_INPUT_LOW: // FSM STATE
begin:
if (input_line = 1'b0)
detect_low; //called task for detecting low

nxt_state <= IDLE;


task detect_low
begin
@(posedge clk)
for (i=0, i=NO_OF_TIMES_LOW, i++) begin
if (input_line)
break;
end
end

endtask


Now the question is FSM will go to IDLE after detecting low for N times? OR
directly after entering if loop (i.e. if (input_line = 1'b0)) ??

Your inputs are welcome, Kindly suggest. Thanks.


What I am saying about it.
- FSM will directly go to IDLE state after detecting if loop, But that is not my intention here.

So what to do? I have to change the code like this

*****************************************************
task detect_low // Modified task
begin
@(posedge clk)
for (i=0, i=NO_OF_TIMES_LOW, i++) begin
if (input_line)
break;
else
signal_a = 1'b1;
end

if (signal_a)
signal_b = 1'b1;

end
endtask

Receive_INPUT_LOW: // Modified FSM STATE
begin:
if (input_line = 1'b0)
detect_low; //called task for detecting low

if (signal_b)
nxt_state <= IDLE;

******************************************************

Is it correct? Is this method is correct? pls share your inputs/comments

Thank you..

 

[gurucharapathy]

if (input_line = 1'b0)
detect_low; //called task for detecting low

nxt_state <= IDLE;

If the three lines above are in exact order as in your code, then the next state will be IDLE, irrespective of the if statement. The if statement being true would only delay the entry into IDLE state by the clock cycles in the detect_low task.
Also why are you checking for low multiple times in the same clockedge ? Shouldn't the clock edge be within the for loop ? My two cents anyway.