simulation problem with rf transistors

[jimito13]

Hi everyone,

I am facing a strange problem with the rf transistors of IBM cms9flp design kit.I have designed a folded cascode OTA with the regular fets (nfets & pfets from cms9flp library) and i want to test this design with the respective rf fets of the rf9flp library.When i substitute all transistors of the design with the respective rf version (except the current sinks circled on the image below) and simulate i take the same ac responce approximately.When i implement those current sinks with rf fets as well and simulate i notice that the design collapses (different dc operating point and ac response...).Why this happens??If more information is needed for this matter to be solved i will provide it.I should note that obviously i have the same transistor dimensions and fingers for both regular and rf version of the current sinks.

I would appreciate any helpful answer.

Thanks in advance,
Jimito13

 

[dick_freebird]

Check the OP bias point, drain current across the type-
swap on the current sink devices.

Maybe you are not getting the W/L equivalence you think.
Maybe the master for that mirror needs to be changed to
RF type as well, at the least. Folded cascodes can be
fussy about current range setting.

 

[jimito13]

I set the dimensions to be let's say W/L with some fingers in both cases with W/L and number of fingers stay constant in both situations (regular and RF).The "master of that mirror",in my testbench,is an ideal CMFB (vcvs) with sufficient gain so i can't change it's type.What else could be the cause of this problem??

 

[dick_freebird]

What do you see for the output common mode voltage,
the mirror gate voltage, the mirror operating point ID?
The clue has to be in there somewhere.

 

[jimito13]

For the regular fets i have : Vout_common=605.9mV with Vref=600mV so for Acmfb_ideal=100 => Vcmfb=590mV

For the RF fets i have : Vout_common=681mV approximately with Vref=600mV so for Acmfb_ideal=100 => Vcmfb=8.1V!! ,thus the total current sinked there is 120mA...but i can't figure out what to do to fix this strange situation..Should i change the RF fet sizing from the initial W/L??If yes,then why only those transistors trigger this problem and not others (for example the above at the folded cascode node) in the design?

 

[dick_freebird]

There is always the possibility of a PDK or model error, I
suppose. What about taking the two believed-identical
flavors and running them side by side in a DC testbench,
looking at ID vs VG, ID vs VD curve families?

Maybe the netlister swaps W for L, or something silly.

However I wouldn't discount the possibility that the
problem lies upstream, and some small difference in
transistor attributes has put you on the wrong side
of some other bias setpoint like the diff pair throwing
too much current for the sink sizing to handle, etc.
There are a lot of externalities to that block, any of
which could bug it. Maybe you want a few less bias
loops to begin with, or pin the ones that you think
you know proper points for.

 

[jimito13]

I will run the dc testbench you proposed me and see what can i conclude...

I have already gone through these thoughts but...why when all the transistors in the design are the RF fets and the sinks are the regular fets everything works perfectly as desired and when the sinks changed to RF type this problem happens??

Thanks for your contribution and the answers.