Simulation problem in Verilog

Hii.i am trying to simulate a verilog code.i am using MODELSIM SE 6.5..but its coming as no design loaded and shows as below..what does it mean

** Error: (vopt-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: stimulus1.v(771): Library xilinxcorelib_ver not found.
# ** Warning: Unable to find library 'xilinxcorelib_ver'.
# ** Error: (vopt-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: stimulus1.v(771): Library unisims_ver not found.
# ** Warning: Unable to find library 'unisims_ver'.
# ** Error: (vopt-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: stimulus1.v(586): Library xilinxcorelib_ver not found.
# ** Warning: Unable to find library 'xilinxcorelib_ver'.
# ** Error: (vopt-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: stimulus1.v(586): Library unisims_ver not found.
# ** Warning: Unable to find library 'unisims_ver'.
# ** Error: (vopt-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: stimulus1.v(33): Library xilinxcorelib_ver not found.
# ** Warning: Unable to find library 'xilinxcorelib_ver'.
# ** Error: (vopt-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: stimulus1.v(33): Library unisims_ver not found.
# ** Warning: Unable to find library 'unisims_ver'.
# ** Error: (vopt-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: stimulus1.v(55): Library xilinxcorelib_ver not found.
# ** Warning: Unable to find library 'xilinxcorelib_ver'.
# ** Error: (vopt-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: stimulus1.v(55): Library unisims_ver not found.
# ** Warning: Unable to find library 'unisims_ver'.
# ** Error: (vopt-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: stimulus1.v(341): Library xilinxcorelib_ver not found.
# ** Warning: Unable to find library 'xilinxcorelib_ver'.
# ** Error: (vopt-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: stimulus1.v(341): Library unisims_ver not found.
# ** Warning: Unable to find library 'unisims_ver'.
# Optimization failed
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./stimulus.fdo PAUSED at line 7

you have to compile, except your design itself:
<XILINX_INSTALL_dir>/ISE/verilog/src/unisims & xilinxcorelib

j.a