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simulation problem in modelsim (vhdl)

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tj.diego

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Hi to all,
i'm studying the vhdl language, and i'm trying to do some exercise!
i did a simple full adder, it works, i have already test it, and with the same criteria i did a ripple carry adder at 8 bits,but i have a problem with the simulation, the error is:

Code:
# Loading work.rcatb(tb)
# ** Warning: (vsim-3473) Component instance "uut : rca_adder" is not bound.
do you have any advice?!View attachment RCA adder.txtView attachment fa-tb.txtView attachment fa.txtView attachment tb-RCA adder.txt

ps i've modified the extension to upload the file!
 

blooz

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Hi to all,
i'm studying the vhdl language, and i'm trying to do some exercise!
i did a simple full adder, it works, i have already test it, and with the same criteria i did a ripple carry adder at 8 bits,but i have a problem with the simulation, the error is:

Code:
# Loading work.rcatb(tb)
# ** Warning: (vsim-3473) Component instance "uut : rca_adder" is not bound.
do you have any advice?!View attachment 55535View attachment 55536View attachment 55537View attachment 55538

ps i've modified the extension to upload the file!
Code:
 library ieee;                           
use ieee.std_logic_1164.all;

entity rcaTB is
end rcaTB;

architecture TB of rcaTB is
  component [B][I][COLOR="red"]rca_8_bit[/COLOR][/I][/B] is
        port(
                        a8,b8:in std_logic_vector(7 downto 0);
                        s8:out std_logic_vector(7 downto 0);
                        cout:out std_logic
        );
end component;
--input
signal tb_a,tb_b: std_logic_vector(7 downto 0);
--output  
signal tb_s:std_logic_vector(7 downto 0);
signal tb_c:std_logic;

begin
  uut:[U][COLOR="red"]rca_8_bit[/COLOR][/U] port map(tb_a,tb_b,tb_s,tb_c);
process
begin
tb_a<="00000000";
tb_b<="00000000";
wait for 20ns;
tb_a<="00011111";
wait for 20ns;
tb_b<="00011111";
wait for 20ns;
tb_a(0)<='1';
wait for 20ns;
tb_b<="00000111";
wait for 20ns;
end process;
end TB;
I have made the slight change to your testbench as highlighted and program Works perfectly without any problem .

---------- Post added at 23:55 ---------- Previous post was at 23:51 ----------

entity rca_8_bit is-- but in test bench the component was referrred as rcaadder ...there was no rca adder entity ...there is only the rca_8_bit ,that's why compiler complainted!
port( a8,b8:in std_logic_vector (7 downto 0);
s8:eek:ut std_logic_vector(7 downto 0);
cout:eek:ut std_logic
);
end rca_8_bit;

architecture structure of rca_8_bit is

component fa
port( a,b,cin :in std_logic;
s,cout :eek:ut std_logic
);
end component;

signal c0,c1,c2,c3,c4,c5,c6,c7:std_logic;
begin
c0<='0';
b_adder0: fa port map (a8(0), b8(0), c0, s8(0), c1);
b_adder1: fa port map (a8(1), b8(1), c1, s8(1), c2);
b_adder2: fa port map (a8(2), b8(2), c2, s8(2), c3);
b_adder3: fa port map (a8(3), b8(3), c3, s8(3), c4);
b_adder4: fa port map (a8(4), b8(4), c4, s8(4), c5);
b_adder5: fa port map (a8(5), b8(5), c5, s8(5), c6);
b_adder6: fa port map (a8(6), b8(6), c6, s8(6), c7);
b_adder7: fa port map (a8(7), b8(7), c7, s8(7), cout);
end structure;
 

tj.diego

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what a stupid error!!!
thanks a lot for your help! :)
 

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