help plz....
I am trying to do simulation of a embedded system designed in xilinx EDK-ISE.Design has a micro blaze soft core instantiated .The application code was large enough to compel us to use an external ram.we are using a st spi memory (m25p16) for configuration as well storing the data of external ram.A small program was stored in bram to transfer this spi memory data into external ram.i compiled all the edk and ise libraries needed.The edk also has provided me the necessary system init file to initialize block ram.I have uploaded the flow that i am following...
Now my problem is that i want to simulate the whole design..for the bram program i got the system_init files from edk simulation model..i wanted to create a simulation model for the ram. i have written the code for the ram memory .Well i have the mcs or hex created from c code.Can somebody tell me how to initialize a vhdl memory model using a mcs or hex file....So that i can initialize the external ram with my program data..
plz...:?:
simulating such a system seem to me like a big headace.
if you have your own ip code then it is reasonable to simulate this device, however i fail to understand why you want to simulate the entire system, which if i understand correctly is xilinx ip cores ?
the best thing is to run your code directly at the target, and use the gdb for debugging !
if you have your own ip code then it is reasonable to simulate this device, however i fail to understand why you want to simulate the entire system, which if i understand correctly is xilinx ip cores ?
the best thing is to run your code directly at the target, and use the gdb for debugging !
No.I am using modelsim.
My design is not limited to microblaze only ....there is another module inside the fpga (its a spartan3e1200) doing a fairly complex job and talking to Ublaze with 7 uarts and two 32 bit gpio's.Yes we are checking the whole design on hardware directly but i find it difficult to get an inside of design.
what i normally do is just simulating my ip (uut) and its enviroment - i.e the different busses attached to the cpu like opb,plb,dcr,npi ...,
and then i stimulate reads and write by cpu to hw or by hw to cpu, including memory acceses.