Simulation of LOAD TRANSIENT ANALYSIS OF LDO

[tompham]

Hi all

I am designing LDO using tsmc 180nm, VDD=1.8v, Vout=1.6v (200mV drop out). I have trouble running load transient response.

If I connect output to a voltage source to generate load current (see attached file) the output transient very good. If I connect output

to current source the spike up and down are quite huge (~400mV). Could anyone tell me which is correct way to run it. Thanks a lot.

 

[crutschow]

The usual test uses a resistive load that is switched in and out. Typically you have a fixed resistive load and switch another resistor in and out to generate a certain percentage change in the load (perhaps 10% to 20% or more).

A current load could also be used as a worst-case test.

A voltage load does not work since a voltage source has zero impedance and thus the output is forced to the value of the source, independent of anything the regulator does. Thus the transient response will look very good since you are looking at the transient response of the voltage source.

 

[tompham]

Hi crutschow

Thanks for reply me. I use a resistive load test as attached file but the spike is around 100mV. I try to reduce to 50mV but not easy task.
Do you have any idea to improve it? My ground current is 10uA at VDD=1.8v. Thanks