simulation of array of integers

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mahmood.n

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The following code performs a dot product on two integer vectors

Package definition
Code:
package dot_product_types is
	type int_vector is array(0 to 7) of integer;
end;
Entity and architecture
Code:
use work.dot_product_types.all;
entity dot_product is
	port( a, b: in int_vector;
		  z: out integer);
end;
architecture beh1 of dot_product is
begin
	process( a, b)
		variable accumulator: integer:=0;
	begin	
		accumulator := 0;
		for i in 0 to 7 loop
			accumulator := accumulator + a(i)*b(i);
		end loop;
		z <= accumulator;
	end process;
end;
The testbench
Code:
use work.dot_product_types.all;
entity dot_product_tb is
end;
architecture x of dot_product_tb is
	component dot_product port( a, b: in int_vector; z: out integer );
	end component;		   
	signal a, b: int_vector;	 
	signal z: integer;
begin	
	u1: dot_product port map( a, b, z );
	process
	begin
		a <= (1, 2, 3, 4, 5, 6, 7, 8);
		b <= (1, 2, 3, 4, 5, 6, 7, 8);
		wait for 10 ns;
		b <= (1, 1, 1, 1, 1, 1, 1, 1);
	end process;
end;
As I run the simulation with activehdl, the result is not meaningful. Although I wrote "wait for", the signals didn't change at 10ns.

P.S: I edited the picture.
 

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Last edited:

This is because you didnt put a wait after the second assignment to b.
Processes loop forever, so at the bottom of the process it loops back and assigns b to (1,2,3,4,5,6,7,8) again without waiting, hence the assignment to 1 is overridden with the original assignment again.
 
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