Simulation of a component that's not fully compiled

8 Simulation
8.1 Testbench
In ./bench/VHDL/ a “self-checking testbench” is provided which runs tests for a default TESTKEYSIZE
is 256 Bit . For different key lengths the constant TESTKEYSIZE has to be changed appropriately.
Expected results for all test cases and key lengths are included. The expected results were
generated by AES Calculator applet, written by Lawrie Brown from ADFA, Canberra Australia
[7]. The testbench consists of a sequence of 5 test cases:
1. load key1, load data1, encrypt : (basic encryption test)
2. key1, data1, decrypt: (basic decryption test)
3. key1, data1, encrypt: (test if internal state was changed)
4. key1, data2, encrypt: (encryption test with new data)
5. key2, data2, encrypt: (encryption test with new key)
8.2 Simulation
The component library is “avs_aes_lib”. All files are expected to be compiled into this library as
all files depend at least on the package avs_aes_lib.avs_aes_pkg.
A Makefile for Mentor Graphics® Modelsim® is given in ./sim/. The default make target simaes

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Code TCL - [expand]
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vlib avs_aes_lib
#vmap work work
set path_rtl "/home/P_9999_00121/iss_a.1/Downloads/avs_aes/trunk/rtl/VHDL/"
 
foreach file [glob -nocomplain -directory $path_rtl *.vhd] {
  vcom -just p -work avs_aes_lib $file
}
foreach file [glob -nocomplain -directory $path_rtl *.vhd] {
  vcom -just e -work avs_aes_lib $file
}
foreach file [glob -nocomplain -directory $path_rtl *.vhd] {
  vcom -just b -work avs_aes_lib $file
}
foreach file [glob -nocomplain -directory $path_rtl *.vhd] {
  vcom -just a -work avs_aes_lib $file
}