simulation not working in modelsim

[goodpranoy]

hi guys,

i am getting these errors and warnings in the transcript

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Process: /tb_top/mapping/data/register_b/line__22 File: C:/Documents and Settings/Pranoy tm/Desktop/qwerty/register_new_collage.vhd
# Break in Process line__22 at C:/Documents and Settings/Pranoy tm/Desktop/qwerty/register_new_collage.vhd line 24


this is the program

---

Code VHDL - [expand]
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library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    
    entity reg_new is
        port( control:in std_logic;
            data_in:in std_logic_vector(7 downto 0);
            reg_enable:in std_logic;
            data_out:out std_logic_vector(7 downto 0);
            a_zero_status:out std_logic;
            clock:in std_logic
            );
        end reg_new;
        
    architecture behav of reg_new is
        subtype cell is std_logic_vector(7 downto 0);
        type memarray is array(0 downto 0) of cell;
        signal mem:memarray;
        begin
            
            process(mem(0))
                begin
                    if(mem(0)="00000000") then
                        a_zero_status<='1';
                        else
                        a_zero_status<='0';
                    end if;
                end process;
                
            process(control,clock)
                      begin
                          if (clock'event and clock='1') then
                          if reg_enable='1' then
                          case control is
                                                      
                            when '1'=>
                            data_out<=mem(0);
                            when '0'=>
                            mem(0)<=data_in;
                            data_out<=(others=>'Z');
                            when others=>
                            data_out<=(others=>'Z');
                        end case;
                    end if;
                end if;
            end process;
        end behav;

---

 

[aruipksni]

hi guys,

i am getting these errors and warnings in the transcript

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Process: /tb_top/mapping/data/register_b/line__22 File: C:/Documents and Settings/Pranoy tm/Desktop/qwerty/register_new_collage.vhd
# Break in Process line__22 at C:/Documents and Settings/Pranoy tm/Desktop/qwerty/register_new_collage.vhd line 24


this is the program

---

Code VHDL - [expand]
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library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    
    entity reg_new is
        port( control:in std_logic;
            data_in:in std_logic_vector(7 downto 0);
            reg_enable:in std_logic;
            data_out:out std_logic_vector(7 downto 0);
            a_zero_status:out std_logic;
            clock:in std_logic
            );
        end reg_new;
        
    architecture behav of reg_new is
        subtype cell is std_logic_vector(7 downto 0);
        type memarray is array(0 downto 0) of cell;
        signal mem:memarray;
        begin
            
            process(mem(0))
                begin
                    if(mem(0)="00000000") then
                        a_zero_status<='1';
                        else
                        a_zero_status<='0';
                    end if;
                end process;
                
            process(control,clock)
                      begin
                          if (clock'event and clock='1') then
                          if reg_enable='1' then
                          case control is
                                                      
                            when '1'=>
                            data_out<=mem(0);
                            when '0'=>
                            mem(0)<=data_in;
                            data_out<=(others=>'Z');
                            when others=>
                            data_out<=(others=>'Z');
                        end case;
                    end if;
                end if;
            end process;
        end behav;

---

in modelsim change
BreakOnAssertion = 3
or from gui gotto simulate - run time options-message sevrity "failure"

 

[TrickyDicky]

You posted a warning, not an error.

That error tells you that some signals are uninitialised when you're using the arithmetic functions. You can supress these specifically with simulation -> runtime options -> suporess messages from synopsis and ieee packages.