appu1985
Member level 2
pls see the output of the signal "pswo"
Code:
module pe(clk,i,x,p,psw,psy,mode,io,xo,po,pswo);
parameter size = 10;//The Image size or the number of pixels in the image
//Input ports of the PROCESSING ELEMENT
input clk;
input [7:0]i;//Index of the input pixel
input [7:0]x;//Value of the pixel input
input [3:0]p;//The Index of the person whose image is being sent
input [4:0]psw;//Partial Sum for weight updating
input [12:0]psy;//Partial Sum for output calculation
input [1:0]mode;//To select the operation as Recognition Phase or Training Phase 00,01- Recognition
//10 - Trainging and Weight Updating 11 - Projection Calculation
//00- Projection Evaluation in Training Phase
//01- Weight Updation in Training Phase
//11 - Recognition Phase
//Output ports of the PROCESSING ELEMENT
output [7:0]io;//The index of the pixel which is evaluated at this PE and going to next PE
output [7:0]xo;//The value of pixel going to next PE
output [3:0]po;//The index value of the person whose image is under processing
output [4:0]pswo;//The calculated the Partial Sum of Weight update sent to next PE as well as stored here
//output [12:0]psyo;//The calculated the Partial Sum of output sent to next PE as well as stored here
//Register Declarations inside the PROCESSING ELEMENT
reg [4:0]w [size:0];//A register in the processig element to store the weights of the Image
reg [12:0]ylearn [15:0];//A register to store the projection "Y" of each image max 16 images
reg [4:0]psw1;//A register to store the partial sum evaluated
reg [12:0]pso1;//A register to store the Partial Sum for evaluating the output projection " Y ".
reg [15:0]count;
//Wire Declaration as used inside the processing element
reg [4:0]t;
reg [12:0]yrcog;
reg [12:0]rectmp;
wire [4:0]w1;
wire [12:0]psj;
wire [4:0]pswo;
//Instantiation of the ckt for the 2nd Step of Weight Update
//Here 'g' is the Partial sum and 'w1' is the Updated weight
//decoder dec(mode,sel);// Adecoder is used just to evaluate the mode of operation
//Initially the logic is selected depending upon the mode of operation
//The below case logic coverts into a Multiplexer
out22 s2(clk,w[i],ylearn[p],x,psw1,w1);
out11 s1(clk,x,w[i],psy,psj);
//First Mode of Operation when the projections are to be evaluated.
always @(x or posedge clk)
begin
count <= count + 1 ;
if(mode == 2'b00 )//It checks if the mode of operation is for Output evaluation
begin
pso1 <= pso1 + psj; //Keeps on accumulating the Partial Sum for Output evaluation
if(count==size)//If one image has passed then it starts assigning the outputs . size is a parmameter holding the image size.
begin
ylearn[p] <= psj;//The Output is assigned
end
end
//Once all the outputs are evaluated the mode is changed to 00 or 01 to Update the weights.
if(mode == 2'b01)//Checks for the mode of operation
begin
t <= w[i]*ylearn[p];
psw1 <= psw + t;//PSW1 accumulates the partial sum of the weight updation formula
//Now for the jth PE if the PS has been evaluattes
w[i] <= w1; //The new updated weight from the Out2 module gets updated
end
end
assign pswo = psw1;// Assigns the value of psw1 to psw whenevr it changes.
//Now we shall operate for the recognition zone.
always @(x or posedge clk)
begin
if(mode == 2'b11)
begin
rectmp <=rectmp + (x * w[i]);
if(i == size)
begin
yrcog <= rectmp;
end
end
end
//Recognition Phase ends here
assign io = i;
assign xo = x;
assign po = p;
endmodule
module out11(clk,xi,w,psi,psj);
input clk;
input [7:0] xi;//The pixel Value input to the PS Calculator
input [7:0] w ;//The weight vector value input to the PS Calculator
input [12:0] psi;//The Input Partial Sum
reg [12:0]m;//The new evaluated output
reg [12:0]psm;
//output [12:0]t;//The output to the Output vector "Y "
output [12:0]psj;//The PS Accumulating register in PE
always @ (clk)
begin
m <= xi * w;
psm <= m + psi;
end
// assign t= m;
assign psj = psm;
endmodule
module out22(clk,w,y,xi,psw,w2);
parameter lrate= 0.01;
input [12:0]y ;
input [7:0] xi;
input [4:0] w ;
input [4:0]psw;
input clk;
reg [12:0]d;
reg [20:0]out;
reg [20:0]temp;
reg [20:0]temp1;
reg [15:0]y2;
reg [20:0]w1;
output [20:0]w2;
wire [20:0]w2;
always @(posedge clk)
begin
d <= lrate * y;
out <= d * xi;
temp <= out + w;
y2 <= w * y ;
temp1 <= psw + y2;
w1 <= temp - temp1;
end
assign w2 = w1;
endmodule