Simulation for Ring Oscillator not working

[rayaprolu]

hi all,

I have written the .V and .tb for multiple ring oscillators for the design as shown in attachment. But the simulation doesn't show the output toggling on each of the 100 ROs. The output is constant at one level. Can someone help me with the correct code.
Thank you.

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Code Verilog - [expand]
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module RO_S(input en, output wire clk);
 
wire out0,out1,out2,out3,out4/* synthesis keep = 1 */;
 
 
//and U0 (out0,en,clk);
//not U1 (out1,out0);
//not U2 (out2,out1);
//not U3 (out3,out2);
//not U4 (out4,out3);
//not U5 (clk,out4);
and U0 (clk,en,out0);
not U1 (out0,out1);
not U2 (out1,out2);
not U3 (out2,out3);
not U4 (out3,out4);
not U5 (out4, clk);
 
endmodule
 
 
 
module ro_25(input en, output wire clk);
wire [24:0] clk_temp;
genvar i;
 
generate
   for (i =0;i<25;i=i+1) begin :tmp
      RO_S U_roi(.en(en),.clk(clk_temp[i]));
   end
endgenerate
 
assign clk = &clk_temp;
endmodule
 
 
 module main(input wire [3:0] i0, input wire [3:0] i1, input wire [3:0] i2, input wire [3:0] i3,
            input wire [3:0] i4, input wire [3:0] i5, input wire [3:0] i6, input wire [3:0] i7,
            input wire [2:0] sel, output wire clk0, output wire clk1, output wire clk2, output wire clk3);
 reg [3:0] mux_out;           
 
   ro_25 U_ro25_0(.en(mux_out[0]),.clk(clk0));
   ro_25 U_ro25_1(.en(mux_out[1]),.clk(clk1));
   ro_25 U_ro25_2(.en(mux_out[2]),.clk(clk2));
   ro_25 U_ro25_3(.en(mux_out[3]),.clk(clk3));
    
     always @(*) begin
      case(sel)
         0: mux_out=i0;
         1: mux_out=i1;
         2: mux_out=i2;
         3: mux_out=i3;
         4: mux_out=i4;
         5: mux_out=i5;
         6: mux_out=i6;
         7: mux_out=i7;
         default: mux_out=i0;
      endcase
   end
endmodule
 
 //how is Wire 'clk' and wire 'clk0/1/2/3' linked?
 //clk_temp=1 for all the 25 ROs in one row.....we have to AND these...instead clk0/1/2/3 are being ANDed??!!

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Following is the testbench:

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module main_tb();
  reg clock;
initial clock =0;
always #10 clock = ~clock;
 
 wire [3:0] i0;
  wire [3:0] i1;
  wire [3:0] i2;
  wire [3:0] i3;
  wire [3:0] i4; 
  wire [3:0] i5; 
  wire [3:0] i6; 
  wire [3:0] i7;
 wire [2:0] sel; 
 wire clk0;
 wire clk1; 
 wire clk2; 
 wire clk3;
 
 
main u_main (  .i0(i0),  .i1(i1),  .i2(i2),  .i3(i3), .i4(i4), .i5(i5), .i6(i6),  .i7(i7),.sel(sel), .clk0(clk0),  .clk1(clk1),  .clk2(clk2), .clk3(clk3));
                
assign i0=4'b0101;
assign i1=4'b0001;
assign i2=4'b1010;
assign i3=4'b1111;
assign i4=4'b0010;
assign i5=4'b0011;
assign i6=4'b0100;
assign i7=4'b1110;
 
assign sel=3'b010;
 
 
 
 
endmodule

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[pfd001]

In general, the ring osc simulation should be done in spice simulator

 

[mrflibble]

A couple of related threads:

https://www.edaboard.com/threads/286765/
https://www.edaboard.com/threads/293817/
https://www.edaboard.com/threads/246615/
https://www.edaboard.com/threads/246360/

No 1:1 answer, but it does contain the various concepts of what you are running into.

- - - Updated - - -

About those synthesis_keep's on wires in your code... Are you sure that will work? Because on xilinx that is a no-go. KEEP attributes do not work on wires, you should place them on registers instead.