[SOLVED] Simulation error in ISE 8.1

[priask]

Hi,

I wrote VHDL code for communication transmitter. I want to test the module using ISE 8.1.

I created a testbench waveform under behavioral simulation. But I am having a problem when I try to
Generate Expected Simulation Results process For the test bench waveform

This is the error that appears every time,

Running Fuse ...
ERROR:Simulator:418 - Compilation failed: vhpcomp: The system cannot find the file specified..


Can anyone suggest how can I solve this problem??

Thanks

 

[mkrtich.nazaryan]

Hi priask, I'm sorry I can't answer your question but I want to ask you something. I'm just installed ISE and want to start learn it, please if you know good guide or tutorial how to start quick use let me know. thanks a lot.

 

[priask]

Hi priask, I'm sorry I can't answer your question but I want to ask you something. I'm just installed ISE and want to start learn it, please if you know good guide or tutorial how to start quick use let me know. thanks a lot.

Hi. I dont know whether you are familiar with vhdl and verilog coding. You can try out "digital VLSI system design" book by S. Ramachandran.
Also I have listed out a few links. you can go through them-
"http://www.strumpen.net/xilinx/tut82i/ise.html"
"http://ece.wpi.edu/~rjduck/Spartan3_Tutorial.pdf"
"http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise11tut.pdf"

Hope these may help you.

 

[mkrtich.nazaryan]

Thanks a lot for your reply. I'm familiar with Verilog HDL and had some projects. Before, I had used ModelSim and Leonardo tools. But Now need to learn Xilinx tools, because recently I bought Spartan3 Starter kit and want to use all it ))

 

[priask]

Hi mkrtich. Its good that you know verilog. I am more familiar with VHDL coding. I have a doubt here regarding verilog coding. I want to write code for keyboard interface. I have a two way signal which we define as inout in VHDL. how do we define it in verilog? Do we write it as "reg" or "wire"? Kindly see if you can help me out.
Thank you

 

[mkrtich.nazaryan]

Dear Pri, actually it's hard to answer this question because I don't know what type of variable you are using. but in 2 worlds: reg can store value and drive strength, wire can't store any value. Reg data type can be driven from initial and always block. So if in your code you are going to assign the value to this variable you need reg:

 

[priask]

Actually the signal I am using is a kibd of buffer in VHDL. The code is a kind of state machine. In few states I am assigning values to this particular variable while in others I am using the same variable for transition condition. So it is acting as a two way signal. for example like a data bus. I hope I am making myself clear here.