simulation diff ASIC Vs FPGA

[masai_mara]

I was asked about the difference in simulation betweeen an asic and an fpga when done at the RTL level. say for example I have the same design(at RTL) one for asic and the other for fpga, is there any difference in how we simulate them for verification?

 

[JesseKing]

i think there is no difference in rtl simulation, because the process independent design is just the advantage of htl.

 

[au_sun]

there is no difference in simulation at RTL level, as JESSE KING stated

u may have the difference at the GATE level when u targeted ur design for ASIC OR FPGA

bcos from GATE level u are doing simulation that are process dependent

 

[icon]

there will not be any difference since simulation is nothing but checking the functionalty of ur written HDL....this is the one of the main advantage of HDL....writing code for various blocks in HDLs are technology independent,....

 

[soccer]

There is no essential difference at RTL simulation. For functional verfication, asic and fpga will give you the same simulation result, but huge distinguish at gate level.

 

[power-twq]

no difference, I think you'll see identical result.

I was asked about the difference in simulation betweeen an asic and an fpga when done at the RTL level. say for example I have the same design(at RTL) one for asic and the other for fpga, is there any difference in how we simulate them for verification?