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Simulation Debugging(0/1 mismatch)

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tyuga454

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Hi,

How are you going to debug the 0/1 mismatch in pattern simulation.

Can you briefly explain with steps to debug the issue.

Thanks,
Tyuga454
 

Are you talking about a simulation scenario in which ATPG test-patterns are fed in to the design through some test-bench?
 

dpaul said:
Are you talking about a simulation scenario in which ATPG test-patterns are fed in to the design through some test-bench?
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Yes..I am talking about DFT simulation in which we do the simulation debugging.

scenario is like expected to be 0 was 1.
 

tyuga454 said:
Yes..I am talking about DFT simulation in which we do the simulation debugging.

scenario is like expected to be 0 was 1.
Click to expand...

Can you please tell us that which pattern is failing like chain test(flush), logic or transition patterns?

1st step is to check the setup is proper or not? like clock is properly generating or not? reset is properly initialized or not.

Are you doing with timing simulation or w/o timing simulation?
 

Hi Maulin,

we are doing timing simulation for SAF and the logic pattern is failing. Setup looks like okay.
 

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