Simulation ans synthesis in Quartus II vs Modelsim

[shnuk]

Hey all,

I wrote Verilog code in modelsim that describe clock divider to 5, I did a simulation to verify that the code is right.
Then I took this code to Quartus in order to see RTL schematic. in order to see RTL schematic I should change the code, the code I wrote didn't pass synthesis.
I have 2 always codes controlled the same output. In modelsim it works fine, in Quartus it didn't, sensitive list I changes to from always@(poedge clock, reset) to always@(poedge clock, negedge reset).

Why there is a different?
does the code I wrote for Altera FPGA will work with Xillinx too?


What is the difference between "ModelSim-Altera 6.1g (Quartus II 7.2) Web Edition" and "Modelsim SE 6.6b"?


Thanks ahead

 

[vipinlal]

May not be the exact answer to your questions, but I will note down some points:

1)Every code which is works in simulation is not sure to pass synthesis.Simulation is more of software nature(like C or some other high level language) but during synthesis if the synthesis tool is not able to create the hardware equivalent for your HDL code then it will fail.
For example "wait for 100 ns" works fine is simulation but fails in synthesis because the tool is not able to find a equivalent hardware circuit for the delay.

2)The code you write for quartus fpga will work on xilinx fpga most of the time. But it should be a plain VHDL code. I mean you shouldnt use vendom specific attributes or other components in the code.Then it will not work.

3)Try to think in terms of hardware when you write a VHDL code. Double edge flip flops are not available in FPGA , so make sure your code doesnt need any thing like that.

--vipin
https://vhdlguru.blogspot.com/

 

[permute]

Simulation ans synthesis in qu(at)rtus II vs Modelsim

Generally, vendors like "negedge reset". Not sure on the exact reasons, but I suspect the "posedge reset" case becomes difficult if reset is evaluated as having a value of 1. (for an active low reset).

In general, FPGAs have special resources used for clocking. For high clock rates, these should be used. Its possible Xilinx/Altera will be able to infer something, but its best to make sure.